Interface latch for data level transfer
    3.
    发明公开
    Interface latch for data level transfer 有权
    SchnittstellenverriegelungfürDatenpegelübertragung

    公开(公告)号:EP1184983A1

    公开(公告)日:2002-03-06

    申请号:EP00830595.5

    申请日:2000-08-31

    Abstract: The invention comprises an interface for translating data of different voltages. It includes an input terminal (52) structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface. A first circuit portion is powered by a power supply having the first voltage level (SUPPLYLOW). A second circuit portion is powered by a power supply having a second voltage level (SUPPLYHIGH). The invention advantageously comprises a power supply detection circuit (M20, M21) structured to accept a detection signal (VCCOFF). This detection circuit is coupled to the first and second circuit portions and structured to maintain a correct output at the output terminal (62) even after the power supply having the first voltage level (SUPPLYLOW) no longer supplies the first voltage level to the interface.

    Abstract translation: 本发明包括用于转换不同电压的数据的接口。 它包括一个输入端(52),其被构造为接受来自由具有第一电压电平的电源提供的电路的输入,以及被构造成提供来自该接口的输出的输出端。 第一电路部分由具有第一电压电平(SUPPLYLOW)的电源供电。 第二电路部分由具有第二电压电平(SUPPLYHIGH)的电源供电。 本发明有利地包括被构造为接受检测信号(VCCOFF)的电源检测电路(M20,M21)。 即使在具有第一电压电平(SUPPLYLOW)的电源不再向接口提供第一电压电平之后,该检测电路耦合到第一和第二电路部分并被构造为在输出端子(62)处保持正确的输出。

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