公开(公告)号：EP1291924A1

公开(公告)日：2003-03-12

申请号：EP01830574.8

申请日：2001-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Ponza, Anna ,  Gallerano, Antonio

IPC: H01L29/78 ,  H01L29/41 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238

Abstract: An MOS electronic device (30) including: a drain region (31); a field insulating layer (33), covering the drain region; an opening (38) in the field insulating layer delimiting an active area (34); a body region (40) housed in the active area; a source region (41) housed in the body region. A portion of the body region comprised between the drain region and the source region forms a channel region (43). A polycrystalline silicon structure (45) extends along the edge of the opening delimiting the active area, partially on top of the field insulating layer and partially on top of the active layer. The polycrystalline silicon structure (45) comprises a gate region (46) extending along a first portion of the edge on top of the channel region (43) and partially surrounding the source region (41) and a non-operative region (47) extending along a second portion of the edge, electrically insulated and at a distance from the gate region, so as to reduce the drain/gate capacity and to increase the cutoff frequency of the MOS device.

Abstract translation: 一种MOS电子器件（30），包括：漏极区域（31）; 场绝缘层（33），覆盖所述漏区; 限定有源区域（34）的场绝缘层中的开口（38）; 容纳在所述活动区域中的身体区域（40） 容纳在身体区域中的源区域（41）。 包括在漏极区域和源极区域之间的体区的一部分形成沟道区域（43）。 多晶硅结构（45）沿着限定有源区的开口的边缘延伸，部分地在场绝缘层的顶部上并部分地在有源层的顶部上延伸。 多晶硅结构（45）包括沿沟道区域（43）的顶部上的边缘的第一部分延伸并且部分地围绕源极区域（41）的一个栅极区域（46）和一个非操作区域（47） 沿着边缘的第二部分电绝缘并且离开栅极区一定距离，以便降低漏极/栅极容量并增加MOS器件的截止频率。