公开(公告)号：EP2933925B1

公开(公告)日：2018-03-28

申请号：EP15163376.5

申请日：2015-04-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giacomini, Mauro ,  Burgio, Carmelo

IPC: H03M1/10 ,  H03M1/46 ,  H03M1/68 ,  H03M1/80

CPC classification number: H03M1/0809 ,  H03M1/1033 ,  H03M1/1057 ,  H03M1/1245 ,  H03M1/464 ,  H03M1/466 ,  H03M1/687 ,  H03M1/804 ,  H03M1/806

Abstract: The present disclosure relates to a method of calibrating a thermometer-code SAR-A/D converter, said thermometer-code SAR-A/D converter comprising a N bit -bit digital-to-analog converter (DAC) for outputting a N bit -bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C MSB ) having a plurality of N Th thermometer elements T j (1) and a second subconverter (C LSB ) having a plurality of N Bin binary-weighted elements (2), wherein said N bit output code is equal to the sum of N BitTh and N BitBin where N Th = 2^N BitTh and N BitBin is equal to N Bin = N BitBin . The calibration method includes the steps of determining (5) an Integral Non-Linearity error value (µ R ) of a R th thermometer-code level of said thermometer elements T j according to the formula: µ R = ˆ‘ j = 0 R - 1 E j - R N th ˆ‘ j = 0 N th - 1 E j where E j represents the relative differences between said plurality of thermometer elements T j and a reference thermometer element T ref selected from said plurality of thermometer elements T j of said digital-to-analog converter (DAC) - minimizing (6) the maximum of said error value µ R to obtain a minimized error value; - generating (7) said output code (OUTPUT) according to said minimized error.

公开(公告)号：EP2541769B1

公开(公告)日：2014-02-26

申请号：EP12167144.0

申请日：2012-05-08

Applicant: STMicroelectronics S.r.l.

Inventor： Giacomini, Mauro

IPC: H03K3/011 ,  H03K3/0231 ,  H03K3/354

CPC classification number: H03K3/0231 ,  H03K3/011 ,  H03K3/354 ,  H03K4/501

公开(公告)号：EP2288033A1

公开(公告)日：2011-02-23

申请号：EP10172719.6

申请日：2010-08-13

Applicant: STMicroelectronics S.r.l.

Inventor： Farabegolo, Gianluca ,  Giacomini, Mauro ,  Losi, Marco

IPC: H03M1/10

CPC classification number: H03M1/1076 ,  H03M1/109 ,  H03M1/468

Abstract: It is described a successive approximation analog-to-digital converter (1). The analog-to-digital converter comprises a first generator (20) of a first analog value (S6) according to a configuration signal (S3), when the analog-to-digital converter is operating in a first phase (t 0 , t 1 , t 2 , t 3 , t 4 ) of a test mode, comprises a digital-to-analog converter (40) adapted to generate a second analog value (S7) according to a control signal (S1), when the analog-to-digital converter is operating in a second phase (t 5 , t 6 , t 7 , t 8 ) of the test mode, comprises a second generator (30), from the comparison of the first analog value with respect to the second analog value, of a digital value (S N ) according to a successive-approximation algorithm, when the analog-to-digital converter is operating in the second phase of the test mode. The analog-to-digital converter further comprises a controller (50) adapted to receive a signal (S4) indicating the test mode; the controller is adapted to generate in the first phase the configuration signal (S3), is adapted to receive in the second phase the digital value (S N ) and generate therefrom the control signal (S1) for controlling the generation of the second analog value according to the successive-approximation algorithm, and it is adapted to generate, from the digital value, an alarm signal (S5) indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

Abstract translation: 描述了逐次逼近模数转换器（1）。 模数转换器包括根据配置信号（S3）的第一模拟值（S6）的第一发生器（20），当模数转换器工作在第一相位（t 0，t 1，t 2，t 3，t 4）包括适于根据控制信号（S1）产生第二模拟值（S7）的数模转换器（40），当模拟 - 数字转换器在测试模式的第二阶段（t 5，t 6，t 7，t 8）中操作，包括第二发生器（30），从第一模拟值相对于第二模拟 当模拟 - 数字转换器在测试模式的第二阶段中工作时，根据逐次逼近算法的数字值（SN）的值。 模数转换器还包括适于接收指示测试模式的信号（S4）的控制器（50）; 控制器适于在第一阶段生成配置信号（S3），适于在第二阶段接收数字值（SN）并从其生成用于控制第二模拟值的产生的控制信号（S1），该控制信号 到逐次逼近算法，并且其适于从数字值产生指示模数转换器内的故障的报警信号（S5），或指示模数转换器的性能的劣化 转换器。

公开(公告)号：EP2933925A1

公开(公告)日：2015-10-21

申请号：EP15163376.5

申请日：2015-04-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giacomini, Mauro ,  Burgio, Carmelo

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/0809 ,  H03M1/1033 ,  H03M1/1057 ,  H03M1/1245 ,  H03M1/464 ,  H03M1/466 ,  H03M1/687 ,  H03M1/804 ,  H03M1/806

Abstract: The present disclosure relates to a method of calibrating a thermometer-code SAR-A/D converter, said thermometer-code SAR-A/D converter comprising a N bit -bit digital-to-analog converter (DAC) for outputting a N bit -bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C MSB ) having a plurality of N Th thermometer elements T j (1) and a second subconverter (C LSB ) having a plurality of N Bin binary-weighted elements (2), wherein said N bit output code is equal to the sum of N BitTh and N BitBin where N Th = 2^N BitTh and N BitBin is equal to N Bin = N BitBin . The calibration method includes the steps of determining (5) an Integral Non-Linearity error value (ε R ) of a R th thermometer-code level of said thermometer elements T j according to the formula: ε R = ∑ j = 0 R - 1 E j - R N th ∑ j = 0 N th - 1 E j where E j represents the relative differences between said plurality of thermometer elements T j and a reference thermometer element T ref selected from said plurality of thermometer elements T j of said digital-to-analog converter (DAC)
- minimizing (6) the maximum of said error value ε R to obtain a minimized error value;
- generating (7) said output code (OUTPUT) according to said minimized error.

Abstract translation: 本发明涉及一种校准温度计代码SAR A / D转换器的方法，所述温度计代码SAR A / D转换器，包括N个比特位的数字 - 模拟输出婷N个位转换器（DAC） 位输出代码，所述数字 - 模拟转换器（DAC），包括第一子转换器具有N个滨的多元性（C MSB）具有第n个温度计元件T J（1）的多元和第二子转换器（C LSB） 二进制加权元件（2），worin所述n位输出码等于N和N第一点BitBin的总和，其中N TH = 2 ^ N第一点和N BitBin等于N = N滨BitBin。 该校准方法包括确定性开采（5），以积分非线性误差值（μR）一个R TH。所述温度计元件T J雅丁的温度计代码级式的步骤：μR =“J = 0 R - 图1e的J - RN个“J = 0第N - 1个C j，其中ëĴdarstellt温度计元件T j和从参考选择的参考温度计元素T的所述多个之间的相对差异所述TJ的温度计元件的多元性 所述数字 - 模拟转换器（DAC） - 最小化（6）的最大所述误差值的率μr，以获得最小化的误差值; - 生成（7）所述输出码（OUTPUT）雅丁于所述的最小化误差。

公开(公告)号：EP2541769A1

公开(公告)日：2013-01-02

申请号：EP12167144.0

申请日：2012-05-08

Applicant: STMicroelectronics S.r.l.

Inventor： Giacomini, Mauro

IPC: H03K3/011 ,  H03K3/0231 ,  H03K3/354

CPC classification number: H03K3/0231 ,  H03K3/011 ,  H03K3/354 ,  H03K4/501

Abstract: It is described an oscillator circuit (1) comprising a first capacitor (c1) provided with a first terminal (16); a resistor (r) provided with a reference terminal (18); a first current generator (g1) provided with a connection terminal (14); a second current generator (g2) provided with a second connection terminal (15). Further, the circuit comprises a switching matrix (13) between the first (g1) and second generators (g2) and resistor (r) and the at least one first capacitor (c1).

Abstract translation: 描述了包括设置有第一端子（16）的第一电容器（c1）的振荡器电路（1） 设置有参考端子（18）的电阻器（r）; 设置有连接端子（14）的第一电流发生器（g1）; 具有第二连接端子（15）的第二电流发生器（g2）。 此外，电路包括在第一（g1）和第二发生器（g2）和电阻器（r）和至少一个第一电容器（c1）之间的开关矩阵（13）。

公开(公告)号：EP1229553A1

公开(公告)日：2002-08-07

申请号：EP01830068.1

申请日：2001-02-05

Applicant: STMicroelectronics S.r.l.

Inventor： Babudri, Irene ,  Giacomini, Mauro

IPC: G11C29/00 ,  G11C16/26

CPC classification number: G11C29/24 ,  G11C16/28

Abstract: The present invention relates to a testing method of a reading operation in a memory device, which method comprises the steps of:

providing first (C1) and second (C2) additional memory cells whose threshold voltage values correspond to a maximum value (S1) and a minimum value (S2) of a distribution of threshold voltages of a cell array (2) of the memory device (1);
programming the first (C1) and second (C2) additional memory cells with predetermined first and second logic values;
simultaneously reading a logic contents of the first (C1) and second (C2) additional memory cells, and data (D1) to be read in the cell array (2);
comparing the logic contents of the first (C1) and second (C2) additional memory cells, as read during the reading step, with the first and second predetermined logic values;
generating a result signal (RES) of the comparison step, such a result signal (RES) having a first value (POS) in the event of the logic contents of the first (C1) and second (C2) additional memory cells, as read during the reading step, matching the first and second predetermined logic values, respectively, and having a second value (NEG) in the event of the logic contents of the first (C1) and second (C2) additional memory cells, as read during the reading step, failing to match the first and second predetermined logic values, respectively.

The invention further relates to a memory device implementing the above testing method.

Abstract translation: 本发明涉及存储器件中的读取操作的测试方法，该方法包括以下步骤：提供其阈值电压值对应于最大值（S1）的第一（C1）和第二（C2）附加存储器单元，以及 存储器件（1）的单元阵列（2）的阈值电压分布的最小值（S2）; 以预定的第一和第二逻辑值编程第一（C1）和第二（C2）附加存储器单元; 同时读取第一（C1）和第二（C2）附加存储单元的逻辑内容以及要在单元阵列（2）中读取的数据（D1）; 将在读取步骤中读取的第一（C1）和第二（C2）附加存储器单元的逻辑内容与第一和第二预定逻辑值进行比较; 生成比较步骤的结果信号（RES），在第一（C1）和第二（C2）附加存储器单元的逻辑内容的情况下，具有第一值（POS）的结果信号（RES）被读取 在读取步骤期间，分别匹配第一和第二预定逻辑值，并且在第一（C1）和第二（C2）附加存储器单元的逻辑内容的情况下具有第二值（NEG），如在第 读取步骤，分别不匹配第一和第二预定逻辑值。 本发明还涉及实现上述测试方法的存储器件。