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    System for connecting peripheral devices and having a priority arbitration, particularly in a microcontroller chip emulator
    1.
    发明公开
    System for connecting peripheral devices and having a priority arbitration, particularly in a microcontroller chip emulator 失效
    系统用于与Prioritätarbitrierung连接外围设备，尤其是在一个仿真器Mikrocontollerchip

    公开(公告)号：EP0913941A1

    公开(公告)日：1999-05-06

    申请号：EP97830553.0

    申请日：1997-10-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Losi, Marco ,  Pelagalli, Sergio

    IPC: H03K19/00 ,  G06F13/26

    CPC classification number: G06F13/24

    Abstract: The invention relates to a peripheral devices connecting system with priority arbitration, comprising at least a connection matrix connected to a plurality of peripheral devices (P1,P2,...,Pn) capable of transmitting a signal to be arbitrated, in particular an interrupt enable signal.
    The system of this invention comprises first (DCA) and second (DCB) connection matrices which are connected to each other through a plurality of logic gates (PL1,PL2,...,PLn) having a progressive number of inputs, for parallel transmitting a plurality of signals to be arbitrated, in particular interrupt enable signals (IE01,IE02,...,IE0n) issued from the peripheral devices (P1,P2,...,Pn), the first (DCA) and second (DCB) matrices having respective inputs and outputs connected directly to the plurality of peripheral devices (P1,P2,...,Pn).
    The invention also relates to a special connection matrix for a microcontroller-emulating chip, which includes a peripheral devices connecting system with priority arbitration (1) according to the invention.

    Abstract translation: 本发明涉及连接具有优先级仲裁系统的外围设备，至少包括：连接到外围设备的多个连接矩阵（P1，P2，...，Pn）的能够发送的信号的被仲裁，特别是中断 使能信号。 本发明的系统包括通过逻辑门的多个（PL1，PL2，...，PLN），其具有的输入端渐进数目，发射并联连接的第一海誓山盟（DCA）和第二（DCB）连接矩阵 的信号的多个来进行仲裁，在特定的中断使能信号（IE01，IE02，...，IE0n）从所述外围装置（P1，P2，...，Pn）的，发出第（DCA）和第二（DCB ）矩阵具有直接连接至外围设备（P1，P2，...，Pn）的的多元性respectivement输入和输出。 因此本发明涉及一种用于微控制器的模拟芯片，其包括连接系统具有优先级仲裁（1）gemäß本发明的外围设备特殊的连接矩阵。

    Successive approximation analog-to-digital converter
    2.
    发明公开
    Successive approximation analog-to-digital converter 有权
    Analog-Digital-Wandler mit schrittweiserAnnäherung

    公开(公告)号：EP2288033A1

    公开(公告)日：2011-02-23

    申请号：EP10172719.6

    申请日：2010-08-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Farabegolo, Gianluca ,  Giacomini, Mauro ,  Losi, Marco

    IPC: H03M1/10

    CPC classification number: H03M1/1076 ,  H03M1/109 ,  H03M1/468

    Abstract: It is described a successive approximation analog-to-digital converter (1). The analog-to-digital converter comprises a first generator (20) of a first analog value (S6) according to a configuration signal (S3), when the analog-to-digital converter is operating in a first phase (t 0 , t 1 , t 2 , t 3 , t 4 ) of a test mode, comprises a digital-to-analog converter (40) adapted to generate a second analog value (S7) according to a control signal (S1), when the analog-to-digital converter is operating in a second phase (t 5 , t 6 , t 7 , t 8 ) of the test mode, comprises a second generator (30), from the comparison of the first analog value with respect to the second analog value, of a digital value (S N ) according to a successive-approximation algorithm, when the analog-to-digital converter is operating in the second phase of the test mode. The analog-to-digital converter further comprises a controller (50) adapted to receive a signal (S4) indicating the test mode; the controller is adapted to generate in the first phase the configuration signal (S3), is adapted to receive in the second phase the digital value (S N ) and generate therefrom the control signal (S1) for controlling the generation of the second analog value according to the successive-approximation algorithm, and it is adapted to generate, from the digital value, an alarm signal (S5) indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

    Abstract translation: 描述了逐次逼近模数转换器（1）。 模数转换器包括根据配置信号（S3）的第一模拟值（S6）的第一发生器（20），当模数转换器工作在第一相位（t 0，t 1，t 2，t 3，t 4）包括适于根据控制信号（S1）产生第二模拟值（S7）的数模转换器（40），当模拟 - 数字转换器在测试模式的第二阶段（t 5，t 6，t 7，t 8）中操作，包括第二发生器（30），从第一模拟值相对于第二模拟 当模拟 - 数字转换器在测试模式的第二阶段中工作时，根据逐次逼近算法的数字值（SN）的值。 模数转换器还包括适于接收指示测试模式的信号（S4）的控制器（50）; 控制器适于在第一阶段生成配置信号（S3），适于在第二阶段接收数字值（SN）并从其生成用于控制第二模拟值的产生的控制信号（S1），该控制信号 到逐次逼近算法，并且其适于从数字值产生指示模数转换器内的故障的报警信号（S5），或指示模数转换器的性能的劣化 转换器。

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