公开(公告)号：EP1583242B1

公开(公告)日：2007-06-06

申请号：EP04425242.7

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/466

公开(公告)号：EP1583244A1

公开(公告)日：2005-10-05

申请号：EP04425241.9

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/46

CPC classification number: H03M1/002 ,  H03M1/462

Abstract: The described converter comprises switched-capacitor quantization means (DAC, COMP) for receiving an analog quantity to be converted (VIN), a register (REG) for a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register (REG) the digital quantity to be furnished as output (OUTBUS). With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator (CLK-GEN) comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals (REGBUS0, REGBUS1) emitted by the logic means.
Also described is a method of using the converter that comprises the following phases: loading of the analog quantity (VIN) in the quantization means (DAC, COMP), memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means (LOG).

公开(公告)号：EP1887702B1

公开(公告)日：2009-07-15

申请号：EP06425570.6

申请日：2006-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/46 ,  H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

公开(公告)号：EP1887702A1

公开(公告)日：2008-02-13

申请号：EP06425570.6

申请日：2006-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/46 ,  H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: An analog digital converter (41) for converting an analog signal (V INP ,V INM ) into a digital output code (D OUT ), comprising:
- a local digital analog converter (42) including at least one segmented array (AR P ,AR M ) comprising an upper segment (AR UP ,AR UM ) and a lower segment (AR LP ,AR LM ) of conversion elements selectively operable by means of respective command codes (CMD COD ) for varying, according to binary weighted contributions, the voltage of a first common node (NS UP ,NS UM ) and the voltage of a second common node (NS LP ,NS LM ) respectively,
- a logic unit (3) to generate digital command codes (CMD COD ) so as to control the local digital/analog converter (42) according to the successive approximation technique for producing the digital output code (D OUT ).
The converter (41) includes redistribution means (46) such as to modify the command codes for redistributing the command codes between the lower segment and the upper segment, making use of at least one auxiliary conversion element (C U1 ,C U2 ) provided in the upper segment.

Abstract translation: 一种用于将模拟信号（V INP，V INM）转换为数字输出代码（D OUT）的模拟数字转换器（41），包括： - 本地数字模拟转换器（42），包括至少一个分段阵列（AR P， AR M）包括通过相应的命令码（CMD COD）选择性地操作的转换元件的上段（AR UP，AR UM）和下段（AR LP，AR LM），用于根据二进制加权贡献来改变 第一公共节点（NS UP，NS UM）的电压和第二公共节点（NS LP，NS LM）的电压分别为产生数字命令码（CMD COD）以便控制的逻辑单元（3） 本地数字/模拟转换器（42）根据用于产生数字输出代码（D OUT）的逐次逼近技术。 转换器（41）包括再分配装置（46），以便利用至少一个辅助转换元件（C U1，C U2）修改用于在下部段和上部段之间重新分配命令代码的命令代码 上段。

公开(公告)号：EP1583244B1

公开(公告)日：2007-06-20

申请号：EP04425241.9

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/46

CPC classification number: H03M1/002 ,  H03M1/462

公开(公告)号：EP1583242A1

公开(公告)日：2005-10-05

申请号：EP04425242.7

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/466

Abstract: The described analog-digital converter comprises quantization means (DAC, COMP) having an input for receiving an analog quantity to be converted (VIN), a register (REG) having an output (OUTBUS) for providing a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) connected to the quantization means (DAC, COMP), the register (REG) and the timing pulse generator (CLK-GEN) and capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register (REG) the digital quantity to be provided at the output (OUTBUS).
With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator (CLK-GEN), which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input (STOP) and the logic means are capable of generating a stop signal (RESOSC) of the oscillator and comprise means (MONOST, OR) for generating the binary signal to be applied to the activation input (STOP) of the oscillator (CLK-GEN). This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal (CONVREQ) and the stop signal (RESOSC) of the oscillator.

Abstract translation: 所描述的模数转换器包括具有用于接收待转换的模拟量（VIN）的输入的量化装置（DAC，COMP），具有用于提供与模拟量对应的数字量的输出（OUTBUS）的寄存器（RE​​G） ，连接到量化装置（DAC，COMP），寄存器（RE​​G）和定时脉冲发生器（CLK-GEN）并能够响应转换请求的定时脉冲发生器（CLK-GEN）和逻辑装置 信号（CONVREQ）通过激活量化装置以使它们执行由定时脉冲定时的预定操作并将要在输出端（OUTBUS）提供的数字量加载到寄存器（RE​​G）中来实现。 为了即使当系统时钟不可用时也允许转换器起作用，集成在包括转换器的其余部分的集成电路中的定时脉冲发生器（CLK-GEN）包括能够被启动的振荡器 /由施加到其激活输入（STOP）的二进制信号停止，并且该逻辑装置能够产生该振荡器的停止信号（RESOSC）并且包括用于产生将被应用于激活的二进制信号的装置（MONOST，OR） 振荡器的输入（STOP）（CLK-GEN）。 该信号呈现分别对应于振荡器响应于振荡器的转换请求信号（CONVREQ）和停止信号（RESOSC）的激活和去激活的第一或第二二进制状态。