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    Current steering digital-analog converter particularly insensitive to packaging stresses
    2.
    发明公开
    Current steering digital-analog converter particularly insensitive to packaging stresses 有权
    Stromgesteuerter数字模拟Wandler besonders unempfindlichgegenüberGehäusespannungen

    公开(公告)号：EP2026467A1

    公开(公告)日：2009-02-18

    申请号：EP07425478.0

    申请日：2007-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Martignone, Riccardo

    IPC: H03M1/06

    CPC classification number: H03M1/0648 ,  H03M1/687 ,  H03M1/747

    Abstract: A current steering digital-analog converter (1) for converting a digital code (In-cod) into an analog signal (Vout) is described. The converter comprises:
    - a substrate of semiconductor material;
    - an array (2) of current generators (MD0, MD1, M1-M15) integrated in the substrate;
    - a common summation node (NC1) and switching means (3) controllable on the basis of the digital code for connecting/disconnecting the current generators (MD0, MD1, M1-M15) to/from the common summation node (NC1).
    The current generators (MD0, MD1, M1-M15) are such as to provide the common summation node (NC1) with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator (MD0) of the array (2) of generators (MD0, MD1, M1-M15).
    The current generator (MD0) is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

    Abstract translation: 描述用于将数字代码（In-cod）转换为模拟信号（Vout）的电流转向数模转换器（1）。 该转换器包括： - 半导体材料的衬底; - 集成在基板中的电流发生器（MD0，MD1，M1-M15）的阵列（2） - 根据用于将电流发生器（MD0，MD1，M1-M15）与公共求和节点（NC1）连接/断开的数字代码可控的公共求和节点（NC1）和切换装置（3）。 电流发生器（MD0，MD1，M1-M15）的目的是为了提供公共求和节点（NC1），该电流具有与通过电流提供给求和节点的单位电流值相比的两倍的功率的多个值 发生器（2）的发生器（MD0）（MD0，MD1，M1-M15）。 电流发生器（MD0）被分成至少等于2的彼此并联的基本数量的模块化电流产生元件。

    Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    3.
    发明公开
    Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 审中-公开
    用于校准集成电路的可调电容的时间常数依赖于电容校准电路

    公开(公告)号：EP1962421A1

    公开(公告)日：2008-08-27

    申请号：EP07425100.0

    申请日：2007-02-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Zamprogno, Marco

    IPC: H03H1/02 ,  H03H7/01

    CPC classification number: H03H1/02 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/043

    Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitor (C var (REG_BUS)) and including a calibration loop (RC_DEL, DFF, TG_SAR) comprising:
    - a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
    - a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
    - a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),

    characterized in that
    said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.

    Abstract translation: 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容器（C VAR（REG_BUS）），并且包括一个校准循环（RC_DEL，DFF，TG_SAR），包括： - 一个可控电容单元（RC_DEL）适合于接收控制信号（SAR_BUS）和包括至少一个 开关电容器（C_AR1，CAR_2）的阵列也可以由控制信号（SAR_BUS），单元（RC_DEL）的方式来激活正被检查，以输出由参数为特征的第一信号（OUT_DEL）上的电容的量根据 由控制信号（SAR_BUS）激活阵列（C_AR1，CAR_2）的; - 一个比较单元（DFF），其适于接收所述第一信号（OUT_DEL）评估是否所述参数是否满足预设条件，并输出比较信号（OUT_DFF）代表评估结果的一个; - 控制和定时逻辑单元（TG_SAR）适合于基于所述比较信号（OUT_DFF）接收比较信号（OUT_DFF）来改变该控制信号（SAR_BUS）表示，在这特点第一信号（OUT_DEL）是一个逻辑信号，并且 所述参数是所述第一信号的时间参数。

    Analog digital converter
    5.
    发明公开
    Analog digital converter 有权
    模拟数字Wandler

    公开(公告)号：EP1887702A1

    公开(公告)日：2008-02-13

    申请号：EP06425570.6

    申请日：2006-08-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

    IPC: H03M1/46 ,  H03M1/06

    CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

    Abstract: An analog digital converter (41) for converting an analog signal (V INP ,V INM ) into a digital output code (D OUT ), comprising:
    - a local digital analog converter (42) including at least one segmented array (AR P ,AR M ) comprising an upper segment (AR UP ,AR UM ) and a lower segment (AR LP ,AR LM ) of conversion elements selectively operable by means of respective command codes (CMD COD ) for varying, according to binary weighted contributions, the voltage of a first common node (NS UP ,NS UM ) and the voltage of a second common node (NS LP ,NS LM ) respectively,
    - a logic unit (3) to generate digital command codes (CMD COD ) so as to control the local digital/analog converter (42) according to the successive approximation technique for producing the digital output code (D OUT ).
    The converter (41) includes redistribution means (46) such as to modify the command codes for redistributing the command codes between the lower segment and the upper segment, making use of at least one auxiliary conversion element (C U1 ,C U2 ) provided in the upper segment.

    Abstract translation: 一种用于将模拟信号（V INP，V INM）转换为数字输出代码（D OUT）的模拟数字转换器（41），包括： - 本地数字模拟转换器（42），包括至少一个分段阵列（AR P， AR M）包括通过相应的命令码（CMD COD）选择性地操作的转换元件的上段（AR UP，AR UM）和下段（AR LP，AR LM），用于根据二进制加权贡献来改变 第一公共节点（NS UP，NS UM）的电压和第二公共节点（NS LP，NS LM）的电压分别为产生数字命令码（CMD COD）以便控制的逻辑单元（3） 本地数字/模拟转换器（42）根据用于产生数字输出代码（D OUT）的逐次逼近技术。 转换器（41）包括再分配装置（46），以便利用至少一个辅助转换元件（C U1，C U2）修改用于在下部段和上部段之间重新分配命令代码的命令代码 上段。

    Switched capacitance circuit
    7.
    发明公开
    Switched capacitance circuit 审中-公开
    Schaltkreis getakteterKapazitäten

    公开(公告)号：EP1594230A1

    公开(公告)日：2005-11-09

    申请号：EP04425319.3

    申请日：2004-05-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco

    IPC: H03M1/00

    CPC classification number: G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

    Abstract: A switched capacitance circuit including:

    a switched capacitance section, receiving an input signal sampling said signal connected to a common node;
    an operational stage, connected to said common node and providing a current to said common node for charging said capacitors during a sampling time interval of said signal.
    The circuit further includes an auxiliary circuit (ANC) connected to said common node and being activated/deactivated for increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

    Abstract translation: 一种开关电容电路，包括：开关电容部分，接收对连接到公共节点的所述信号进行采样的输入信号; 操作级，连接到所述公共节点，并在所述信号的采样时间间隔期间向所述公共节点提供电流以对所述电容器充电。 电路还包括连接到所述公共节点并被激活/去激活的辅助电路（ANC），用于在等于所述采样间隔的一部分的至少一个时间间隔期间增加提供给所述公共节点的电流。

    Analog-digital converter
    8.
    发明公开
    Analog-digital converter 有权
    模数转换器

    公开(公告)号：EP1583242A1

    公开(公告)日：2005-10-05

    申请号：EP04425242.7

    申请日：2004-04-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

    IPC: H03M1/00

    CPC classification number: H03M1/002 ,  H03M1/466

    Abstract: The described analog-digital converter comprises quantization means (DAC, COMP) having an input for receiving an analog quantity to be converted (VIN), a register (REG) having an output (OUTBUS) for providing a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) connected to the quantization means (DAC, COMP), the register (REG) and the timing pulse generator (CLK-GEN) and capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register (REG) the digital quantity to be provided at the output (OUTBUS).
    With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator (CLK-GEN), which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input (STOP) and the logic means are capable of generating a stop signal (RESOSC) of the oscillator and comprise means (MONOST, OR) for generating the binary signal to be applied to the activation input (STOP) of the oscillator (CLK-GEN). This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal (CONVREQ) and the stop signal (RESOSC) of the oscillator.

    Abstract translation: 所描述的模数转换器包括具有用于接收待转换的模拟量（VIN）的输入的量化装置（DAC，COMP），具有用于提供与模拟量对应的数字量的输出（OUTBUS）的寄存器（RE​​G） ，连接到量化装置（DAC，COMP），寄存器（RE​​G）和定时脉冲发生器（CLK-GEN）并能够响应转换请求的定时脉冲发生器（CLK-GEN）和逻辑装置 信号（CONVREQ）通过激活量化装置以使它们执行由定时脉冲定时的预定操作并将要在输出端（OUTBUS）提供的数字量加载到寄存器（RE​​G）中来实现。 为了即使当系统时钟不可用时也允许转换器起作用，集成在包括转换器的其余部分的集成电路中的定时脉冲发生器（CLK-GEN）包括能够被启动的振荡器 /由施加到其激活输入（STOP）的二进制信号停止，并且该逻辑装置能够产生该振荡器的停止信号（RESOSC）并且包括用于产生将被应用于激活的二进制信号的装置（MONOST，OR） 振荡器的输入（STOP）（CLK-GEN）。 该信号呈现分别对应于振荡器响应于振荡器的转换请求信号（CONVREQ）和停止信号（RESOSC）的激活和去激活的第一或第二二进制状态。

    Time-delay circuit
    9.
    发明公开
    Time-delay circuit 审中-公开
    Zeitverzögerungsschaltung

    公开(公告)号：EP1564886A1

    公开(公告)日：2005-08-17

    申请号：EP04425083.5

    申请日：2004-02-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Garibaldi, Federico

    IPC: H03K5/13 ,  H03K5/08

    CPC classification number: H03K5/08 ,  H03K5/13

    Abstract: The described circuit comprises a first stage with an inverter (INV1), a capacitor (C1) connected to the input terminal of the inverter, a constant current generator (G1) and an electronic switch (M1) controlled by an input pulse (IN). The capacitor (C1) begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter (INV1) from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. With a view to obtaining a delay time substantially independent of the inverter threshold, the circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter (INV2) equal to the one of the first stage. The delay time of the circuit is given by the sum of the time needed to charge the capacitor (C1) of the first stage from ground to the threshold voltage and the time needed to discharge the capacitor (C2) of the second stage from the supply voltage (VDD) to the threshold voltage. This sum is independent of the threshold values of the inverters.

    Abstract translation: 所描述的电路包括具有逆变器（INV1）的第一级，连接到逆变器的输入端的电容器（C1），恒定电流发生器（G1）和由输入脉冲（IN）控制的电子开关（M1） 。 电容器（C1）开始在输入脉冲的预定边缘充电，使逆变器（INV1）的输入端从第一电压（接地）转换到逆变器的开关阈值电压，使得在输出端 逆变器获得具有如参照输入脉冲的预定边缘具有取决于逆变器阈值的延迟时间的边缘的脉冲。 为了获得基本上与逆变器阈值相当的延迟时间，电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级的反相器（INV2） 的第一阶段 电路的延迟时间由第一级的接地电容器（C1）向阈值电压充电所需的时间和从供电电路的第二级电容器（C2）放电所需的时间之和给出 电压（VDD）达到阈值电压。 该和与反相器的阈值无关。

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