公开(公告)号：EP0986015B1

公开(公告)日：2003-11-26

申请号：EP98830526.4

申请日：1998-09-09

Applicant: STMicroelectronics S.r.l.

Inventor： Chinosi, Mauro ,  Guardiani Carlo,

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036

公开(公告)号：EP0986015A1

公开(公告)日：2000-03-15

申请号：EP98830526.4

申请日：1998-09-09

Applicant: STMicroelectronics S.r.l.

Inventor： Chinosi, Mauro ,  Guardiani Carlo,

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A method for the electric dynamic simulation of VLSI circuits, the particularity whereof resides in the fact that it comprises the steps of:

-- determining, by means of a digital simulator and starting from a circuit to be simulated, a plurality of independent subcircuits whose dimensions are equal to, or smaller than, those of the circuit;
-- electrically simulating each one of the subcircuits; and
-- concatenating the results obtained by means of the electric simulations of the subcircuits.

Abstract translation: 一种用于VLSI电路的电动态模拟的方法，其特征在于其包括以下步骤： - 通过数字仿真器和从要仿真的电路开始确定多个独立子电路， 尺寸等于或小于电路的尺寸; - 电子模拟每个子电路; 并连接通过电路的电气仿真获得的结果。