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    Method for the electric dynamic simulation of VLSI circuits
    5.
    发明公开
    Method for the electric dynamic simulation of VLSI circuits 有权
    Verfahren zur Dynamischen Elektrischen Simulation von VLSI Schaltungen

    公开(公告)号：EP0986015A1

    公开(公告)日：2000-03-15

    申请号：EP98830526.4

    申请日：1998-09-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Chinosi, Mauro ,  Guardiani Carlo,

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G06F17/5036

    Abstract: A method for the electric dynamic simulation of VLSI circuits, the particularity whereof resides in the fact that it comprises the steps of:

    -- determining, by means of a digital simulator and starting from a circuit to be simulated, a plurality of independent subcircuits whose dimensions are equal to, or smaller than, those of the circuit;
    -- electrically simulating each one of the subcircuits; and
    -- concatenating the results obtained by means of the electric simulations of the subcircuits.

    Abstract translation: 一种用于VLSI电路的电动态模拟的方法，其特征在于其包括以下步骤： - 通过数字仿真器和从要仿真的电路开始确定多个独立子电路， 尺寸等于或小于电路的尺寸; - 电子模拟每个子电路; 并连接通过电路的电气仿真获得的结果。

    A process and system for estimating the power consumption of digital circuits and a computer program product therefor
    7.
    发明公开
    A process and system for estimating the power consumption of digital circuits and a computer program product therefor 有权
    方法以及用于估计数字电路的功率消耗的系统和相关计算机程序产品

    公开(公告)号：EP1205861A1

    公开(公告)日：2002-05-15

    申请号：EP00830735.7

    申请日：2000-11-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Battu, Luca ,  Chinosi, Mauro ,  Sforza, Francesco ,  Brunelli, Marco ,  Castelnuovo, Andrea

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G01R31/3004 ,  G06F2217/78

    Abstract: In order to estimate power consumption, over a given time interval, of digital circuits described at the level of functional elements (G) provided with input/output terminals (a, b, c; x), associated additional elements (B) are emulated at the hardware level. The said additional emulated elements are able to detect, during said time interval, at least one signal indicative of the behaviour of the functional element (G) associated during hardware emulation of the circuit. Preferably the number of transitions performed during the aforesaid time interval of the associated functional element (G) is recorded, as well as the fraction of time in which the state of said functional element (G) is stable (1 or 0). The value of said signals is acquired to perform an estimation of the power consumption of the functional element (G) during the aforesaid time interval.

    Abstract translation: 为了估计功耗，在给定的时间间隔，在设置有输入/输出端子的功能元件（G）的等级上描述数字电路（A，B，C; x）时，相关联的附加元件（B）的模拟 在硬件水平。 所述附加模拟元件能够检测，所述时间间隔期间，指示所述电路的硬件仿真期间相关联的功能元件（G）的行为中的至少一个信号。 优选地，所述相关联的功能元件（G）的上述时间间隔期间执行的转变的数目被记录，以及随着时间的分数，其中，所述功能元件（G）的状态是稳定的（1或0）。 所述信号的值被获取在所述功能元件（G）的功率消耗的估计上述时间间隔期间执行。

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