公开(公告)号：EP1320026A1

公开(公告)日：2003-06-18

申请号：EP01830764.5

申请日：2001-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Kocarev, Ljupco ,  Stojanovski, Toni ,  Rizzotto, Gianguido ,  Italia, Francesco ,  Porto, Domenico

IPC: G06F7/58

CPC classification number: H04L9/0861 ,  G06F7/588

Abstract: A method for generating a random number sequence whose randomness properties are determined a priori , comprises the steps of defining a parametric map; calculating, in function of parameters of the map, the entropy and the Lyapunov exponent of random number sequences obtainable using the parametric map; identifying at least a set of values of parameters for which the entropy and the Lyapunov exponent are positive numbers the map has no attracting point; assigning a pre-established value as a first feedback value and carrying out cyclically the following steps for generating a random number sequence:

(i) determining said parameters inside the set as the numerical values of respective physical quantities;
(ii) outputting a random number, according to said map with the parameters and the assigned feedback value;
(iii) assigning as new feedback value said output random number.

A circuit, preferably realized using a switched current technique, implements the method of the invention for generating a random bit sequence.

Abstract translation: 一种用于生成随机数序列的随机性谁的性质是确定开采先验方法包括定义一个参数图的步骤; 计算，在地图的参数的功能，熵和随机数的Lyapunov指数序列可获得的使用参数图; 确定至少一组为其熵和Lyapunov指数为正数的映射没有吸引点的参数值; 分配预先建立的值作为第一反馈值并进行循环，用于产生一个随机数序列以下步骤：（i）确定的采矿所述设定为物理量respectivement的数值内部参数; （二）输出廷一个随机数，gemäß到所述地图的参数和所分配的反馈值; （三）分配作为新的反馈值，所述输出随机数。 使用开关电流技术的电路，优选地实现，实现本发明的用于产生随机位序列的方法。

公开(公告)号：EP0903955A1

公开(公告)日：1999-03-24

申请号：EP97830438.4

申请日：1997-09-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mazzaglia, Sergio ,  Italia, Francesco ,  Lavorgna, Mario

IPC: H04Q11/04

CPC classification number: H04L1/0083 ,  H04L2012/5616 ,  H04L2012/5647 ,  H04Q11/0478

Abstract: A PET decoder for ATM network has a modular architecture composed of a processing unit ( PU ) having RO M and SRAM memory means and a processing pipeline ( build _ A , LU _ dec , find _ Y , find _ X ) for constructing from a block of m data of a certain number of bits, a square matrix A based on a vector D of relative points over the Galois field (GF[p]), decomposing by triangular factorization the square matrix A and solving the subsystem of equations by simple substitution, and a control unit ( CU ) interfacing with the ATM network, a programmable parallel processor, a random access memory ( RAM ) and said processing unit ( PU ).

Abstract translation: 用于ATM网络的PET解码器具有由具有ROM和SRAM存储器装置的处理单元（PU）和用于从一定数量的数据的m个数据块构建的处理流水线（build_A，LU_dec，find_Y，find_X）组成的模块化架构 位，基于伽罗瓦域（GFÄpÜ）上的相对点的向量D的方阵A，通过三角因子分解方法矩阵A并通过简单替换来求解方程子系统，以及与 ATM网络，可编程并行处理器，随机存取存储器（RAM）和所述处理单元（PU）。

公开(公告)号：EP0994598B1

公开(公告)日：2004-12-29

申请号：EP98830601.5

申请日：1998-10-12

Applicant: STMicroelectronics S.r.l.

Inventor： Italia, Francesco ,  Fortuna, Luigi ,  Beritelli, Francesco ,  Di Cola, Eusebio

IPC: H04L9/00

CPC classification number: H04L9/001 ,  H04L9/0891 ,  H04L9/12 ,  H04L2209/04 ,  H04L2209/125