公开(公告)号：EP0903955A1

公开(公告)日：1999-03-24

申请号：EP97830438.4

申请日：1997-09-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mazzaglia, Sergio ,  Italia, Francesco ,  Lavorgna, Mario

IPC: H04Q11/04

CPC classification number: H04L1/0083 ,  H04L2012/5616 ,  H04L2012/5647 ,  H04Q11/0478

Abstract: A PET decoder for ATM network has a modular architecture composed of a processing unit ( PU ) having RO M and SRAM memory means and a processing pipeline ( build _ A , LU _ dec , find _ Y , find _ X ) for constructing from a block of m data of a certain number of bits, a square matrix A based on a vector D of relative points over the Galois field (GF[p]), decomposing by triangular factorization the square matrix A and solving the subsystem of equations by simple substitution, and a control unit ( CU ) interfacing with the ATM network, a programmable parallel processor, a random access memory ( RAM ) and said processing unit ( PU ).

Abstract translation: 用于ATM网络的PET解码器具有由具有ROM和SRAM存储器装置的处理单元（PU）和用于从一定数量的数据的m个数据块构建的处理流水线（build_A，LU_dec，find_Y，find_X）组成的模块化架构 位，基于伽罗瓦域（GFÄpÜ）上的相对点的向量D的方阵A，通过三角因子分解方法矩阵A并通过简单替换来求解方程子系统，以及与 ATM网络，可编程并行处理器，随机存取存储器（RAM）和所述处理单元（PU）。