公开(公告)号：EP2282406A2

公开(公告)日：2011-02-09

申请号：EP10169807.4

申请日：2010-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Giombanco, Salvatore ,  Grande, Michele ,  Lombardo, Giovanni ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04B1/12

CPC classification number: H04B1/123 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0292

Abstract: There is described a receiver (4) of a signal communication apparatus; the apparatus comprising a transmitter (1) for transmitting the signals, the receiver (4) for receiving the signals and a galvanically isolated wireless interface (3) interposed between the transmitter and the receiver and comprising a transmitting antenna (L1) and a receiving antenna (L2). The receiver comprises a disturbance rejection circuit (6, 52) coupled to the receiving antenna (L2) and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.

Abstract translation: 描述了信号通信设备的接收机（4）; 该装置包括用于发送信号的发射机（1），用于接收信号的接收机（4）和插在发射机和接收机之间的电隔离无线接口（3），包括发射天线（L1）和接收天线 （L2）。 接收机包括耦合到接收天线（L2）的干扰抑制电路（6,52），并且能够以电隔离的输入和输出之间的电势变化补偿在发射天线和接收天线之间流动的寄生电流 接口。

公开(公告)号：EP2282405A2

公开(公告)日：2011-02-09

申请号：EP10169812.4

申请日：2010-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Lombardo, Giovanni ,  Giombanco, Salvatore ,  Grande, Michele ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04B1/10

CPC classification number: H04B1/10

Abstract: There is described a receiver (4) of a signal communication apparatus; the apparatus comprises a transmitter (1) adapted to transmit coded signals, the receiver (4) for receiving the signal and a wireless interface (3) interposed between the transmitter and the receiver and comprising a transmitting antenna (L1) and a receiving antenna (L2). The receiver comprises decoding means (12) of the received signal and first means (9, 10) coupled to the receiving antenna (L2) and capable of triggering said decoding means of the received signal if the value of the received signal is outside a logical hysteresis consisting of a first logic threshold (TH_LO) having a value smaller than the value of the direct current component of the received signal and a second logic threshold (TH_HI) having a value greater than the value of the direct current component (Irde) of the received signal.

Abstract translation: 描述了信号通信设备的接收机（4）; 该装置包括适于发送编码信号的发射机（1），用于接收信号的接收机（4）和插在发射机与接收机之间的无线接口（3），包括发射天线（L1）和接收天线 L2）。 接收机包括接收信号的解码装置（12）和耦合到接收天线（L2）的第一装置（9,10），并且如果接收信号的值在逻辑 具有小于接收信号的直流分量的值的第一逻辑阈值（TH_LO）和具有大于直流分量（Irde）的值的第二逻辑阈值（TH_HI）的第二逻辑阈值 接收信号。

公开(公告)号：EP2280488A1

公开(公告)日：2011-02-02

申请号：EP10167420.8

申请日：2010-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Giombanco, Salvatore ,  Lombardo, Giovanni ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04B1/16 ,  H04L7/033 ,  G06F13/38

CPC classification number: H04B1/16 ,  H04L7/0008 ,  H04L25/0264 ,  H04L25/0268 ,  H04L27/02

Abstract: A transmission and reception apparatus for at least one digital data signal (DATA) is described. The digital data signal is characterized by two logical levels, first and second logical levels, with said second logical level higher than the first logical level. The apparatus comprises a transmitter (6, 1), a receiver (3, 7) and a galvanically isolated wireless interface (5) arranged between the transmitter and the receiver and comprising a transmitting antenna and a receiving antenna formed by a pair of coils; said transmitter, receiver and wireless interface are arranged so as to form a two-level isolated digital channel and the transmitter comprises means (6, 1) adapted to send a synchronization signal (CLOCK) to the receiver. The receiver comprises means (7, 71, 72) adapted to synchronize the receiver and the transmitter by means of the received synchronization signal (CLOCK) and the transmitter comprises further means (62, 61) adapted to send said digital data signal (DATA) upon the synchronization of the receiver and transmitter; the means (7, 71, 72) of the receiver comprising at least one memory element (71) configured to memorize, during the reception of said digital data signal (DATA), the information relative to the received synchronization signal (CLOCK). ( Fig. 6 )

Abstract translation: 描述用于至少一个数字数据信号（DATA）的发送和接收装置。 数字数据信号的特征在于具有高于第一逻辑电平的所述第二逻辑电平的两个逻辑电平的第一和第二逻辑电平。 该装置包括发射机（6,1），接收机（3,7）和布置在发射机和接收机之间的电隔离无线接口（5），并且包括由一对线圈形成的发射天线和接收天线; 所述发射机，接收机和无线接口被布置成形成两级隔离数字信道，并且发射机包括适于向接收机发送同步信号（CLOCK）的装置（6,1）。 接收机包括适于通过所接收的同步信号（CLOCK）使接收机和发射机同步的装置（7,71,72），并且发射机包括适于发送所述数字数据信号（DATA）的另外的装置（62,61） 在接收机和发射机同步时; 所述接收机的装置（7,71,72）包括至少一个存储器元件（71），所述至少一个存储器元件被配置为在所述数字数据信号（DATA）的接收期间存储关于所接收的同步信号（CLOCK）的信息。 （图6）

公开(公告)号：EP2282435A1

公开(公告)日：2011-02-09

申请号：EP10170931.9

申请日：2010-07-27

Applicant: STMicroelectronics S.r.l.

Inventor： Lombardo, Giovanni ,  Giombanco, Salvatore ,  Tumminaro, Salvatore ,  Marino, Filippo

IPC: H04L1/16

CPC classification number: H04L1/1812 ,  H04L1/1896

Abstract: There is described a signal communication apparatus comprising first (51) and second (52) channels for communicating signals between two electronic devices (10, 4); each of said first and second channels comprises a transmitter (1, 21, 22) for transmitting signals, a receiver (3, 24, 25) for receiving signals and an interface (23) arranged between the transmitter and the receiver. The transmitter comprises first means (21, 22) adapted to code the signals in the form of a frame of H bits (F), with H being an integer, and adapted to serially transmit said frame of H bits through said interface, and the receiver comprises a decoder (25) for decoding said frame of H bits, said frame of H bits comprising P data bits (DATA), K redundancy bits and a sequence of L control bits adapted to identify the type of frame to be transmitted, with L, P and K being integers.

Abstract translation: 描述了一种信号通信设备，包括用于在两个电子设备（10,4）之间传送信号的第一（51）和第二（52）个信道。 所述第一和第二信道中的每一个包括用于发送信号的发射机（1,21,22），用于接收信号的接收机（3,24,25）和布置在发射机和接收机之间的接口（23）。 发射机包括适于以H比特（F）的帧的形式对信号进行编码的第一装置（21,22），其中H是整数，并且适于通过所述接口串行发送所述H比特帧，并且 接收机包括用于解码所述H比特帧的解码器（25），所述H比特比特包括P数据比特（DATA），K个冗余比特和适用于识别要发送的帧类型的L个控制比特序列， L，P和K为整数。