公开(公告)号：EP4239960A1

公开(公告)日：2023-09-06

申请号：EP23156362.8

申请日：2023-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： MINNELLA, Filippo ,  DONZELLI, Gea

IPC: H04L25/02

Abstract: A processing system (10a) is described. The processing system (10a) comprises a UART communication interface (50) managing a transmission and a reception signal according to a given baud rate, and a baud-rate detection circuit (70).
Specifically, an edge detector (700) is configured to generate a first control signal (TRIG) indicating edges in the reception signal (RX). In response to an edge in the reception signal (RX), a digital counter circuit (702) resets a count value (CNT). Conversely, in the absence of edges, the digital counter circuit (702) increases the count value (CNT). Once a new edge is signaled, a validation circuit (704) verifies the count value (CNT). Specifically, when the count value (CNT) is smaller than a maximum value (MAX_CNT), the validation circuit (704) asserts a second control signal (SEL). Otherwise, the validation circuit (704) de-asserts the second control signal.
A register (706; 708) is configured to provide a threshold signal (BIT_CNT) by storing the count value (CNT) when the second control signal (SEL) is asserted. Accordingly, the count value (CNT) indicates the time between two consecutive edges of the reception signal, wherein the validation circuit updates the threshold signal (BIT_CNT) stored by the register only when this time is in a permitted range, e.g. , in order to update the register only in case the time corresponds presumably to the duration of a single bit. Accordingly, the baud rate of the UART communication interface (50) may be determined as a function of the threshold signal (BIT_CNT) stored by the register.

公开(公告)号：EP4087108A1

公开(公告)日：2022-11-09

申请号：EP22169183.5

申请日：2022-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： CASTELLANO, Gerardo ,  PEDONE, Leonardo ,  MINNELLA, Filippo ,  RAIMONDI, Marcello

IPC: H02M3/158 ,  H02M3/157 ,  H02M1/32 ,  H02M1/084 ,  H02M1/38

Abstract: A control circuit (22b) for a multiphase buck converter is disclosed. The control circuit (22b) comprises a regulator circuit (2222) and a plurality of phase control circuits (2220). The regulator circuit (2222) generates a regulation signal ( REG ) as a function of a feedback signal ( FB ) and a reference signal ( V ref ), and each phase control circuit (2220 1 , ..., 2220 n ) is configured to receive a current sense signal ( CS' ) and generate a respective PWM signal ( PWM' ) as a function of the respective current sense signal ( CS' 1 ) and the regulation signal ( REG ) .
In particular, the control circuit (22b) comprises a first selector circuit (30) and a second selector circuit (32) configured to receive a selection signal ( SEL ) and selectively connect each phase control circuit (2220) of a subset of the phase control circuits (2220) to a PWM signal ( PWM ) to be used to drive (220) a respective stage of the multiphase buck converter, and to current sense signal ( CS ) provided by the respective stage of the multiphase buck converter. A selection control circuit (34) generates the selection signal ( SEL ), in order to connect the phase control circuits (2220) to different stages of the multiphase buck converter.

公开(公告)号：EP4071624A1

公开(公告)日：2022-10-12

申请号：EP22163845.5

申请日：2022-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： MINNELLA, Filippo

IPC: G06F13/38 ,  G06F13/40

Abstract: An electronic device (50) comprises a processing unit (500) including a memory (502), a JTAG interface (504) comprising a test data input line and a test mode select line and coupled to the processing unit (500), a bridge circuit (10), and a multiplexer circuit (506). The bridge circuit (10) comprises a serial communication interface configured to receive a serial data input signal (UART_RX) which conveys at least one input serial data frame comprising a set of input binary values. The bridge circuit (10) comprises a serial-to-parallel converter circuit block configured to receive the at least one input serial data frame, process the at least one input serial data frame to read a first subset of input binary values and a second subset of input binary values from the set of input binary values, and transmit the first subset of input binary values via a first output signal (TDI_BR) and transmit the second subset of input binary values via a second output signal ( TMS _ BR ) . The multiplexer circuit (506) is configured to selectively ( SEL_BR ) propagate to the test data input line of the JTAG interface (504) either a test data input signal ( TDI _ PIN ) received at a respective pin (504b) of the electronic device (50) or the first output signal ( TDI _ BR) transmitted by the bridge circuit (10), and selectively propagate to the test mode select line of the JTAG interface (504) either a test mode select signal ( TMS _ PIN) received at a respective pin (504b) of the electronic device (50) or the second output signal ( TMS_BR ) transmitted by the bridge circuit (10).