公开(公告)号：EP4175181A1

公开(公告)日：2023-05-03

申请号：EP22200971.4

申请日：2022-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： PEDONE, Leonardo ,  SCADUTO, Simone ,  GAUDIANO, Rossella ,  BRIVIO, Matteo ,  VENTURELLI, Matteo

IPC: H03M1/10

Abstract: A system for testing comprising an electronic circuit to be tested (11; 11'; 11"; 11‴) and an automatic testing equipment (12; 12'),
said electronic circuit (11; 11'; 11"; 11‴) to be tested comprises a digital to analog converter (111; 111';111"), comprising
a set of electronic components (R; I), in particular arranged in a network, coupled to an analog reference voltage or to an analog reference current and
a multiplexing network of switches (111b) coupled to said set of electronic components (R;I) and configured to select paths in said set of electronic components (R;I) on the basis of digital values (DC) at the input of said digital to analog converter (111; 111';111") supplied by a logic control module (112) comprised in said electronic circuit (11; 11'; 11"; 11‴),
said electronic circuit (11; 11'; 11"; 11‴) to be tested comprising an input data link (113b, 123b) between the automatic testing equipment (20, 20', 20") and the logic control module (112),
the system for testing being configured to perform a test of the set of electronic components (R;I) in which the automatic testing equipment (20, 20', 20") is configured to send digital data (TD) to control the logic module (112) inputting digital codes (DC) in the digital to analog converter (111; 111';111") and measuring the analog output of the digital to analog converter (111; 111';111") by a measuring instrument (122; 122') in said automatic testing equipment (12;12') coupled to an output (VDAC, Vin) of the electronic circuit (10, 10', 10‴), then checking if the measured values matches expected converted values for the given digital data (TD),
wherein said test of the digital to analog converter (111; 111'; 111") comprises a further test of the multiplexing network of switches (111b) in which
said logic module (112) is configured to execute a built-in test sequence (300) comprising supplying by said logic module (112) a sequence of digital codes (DC) forcing given switches of said multiplexing network of switches (111b) in a determined open or close state,
said electronic circuit (11'; 11"; 11‴) comprising a feedback circuit (111d) to supply a feedback signal (FB) to said logic module (112), said logic module (112) being configured, on the basis of said feedback signal (FB), to control an execution flow of the built-in test sequence (300)) and to verify (324, 325) if the feedback signal (TB) matches an expected value for the corresponding digital code (DC) in the sequence of digital codes.

公开(公告)号：EP4087108A1

公开(公告)日：2022-11-09

申请号：EP22169183.5

申请日：2022-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： CASTELLANO, Gerardo ,  PEDONE, Leonardo ,  MINNELLA, Filippo ,  RAIMONDI, Marcello

IPC: H02M3/158 ,  H02M3/157 ,  H02M1/32 ,  H02M1/084 ,  H02M1/38

Abstract: A control circuit (22b) for a multiphase buck converter is disclosed. The control circuit (22b) comprises a regulator circuit (2222) and a plurality of phase control circuits (2220). The regulator circuit (2222) generates a regulation signal ( REG ) as a function of a feedback signal ( FB ) and a reference signal ( V ref ), and each phase control circuit (2220 1 , ..., 2220 n ) is configured to receive a current sense signal ( CS' ) and generate a respective PWM signal ( PWM' ) as a function of the respective current sense signal ( CS' 1 ) and the regulation signal ( REG ) .
In particular, the control circuit (22b) comprises a first selector circuit (30) and a second selector circuit (32) configured to receive a selection signal ( SEL ) and selectively connect each phase control circuit (2220) of a subset of the phase control circuits (2220) to a PWM signal ( PWM ) to be used to drive (220) a respective stage of the multiphase buck converter, and to current sense signal ( CS ) provided by the respective stage of the multiphase buck converter. A selection control circuit (34) generates the selection signal ( SEL ), in order to connect the phase control circuits (2220) to different stages of the multiphase buck converter.

公开(公告)号：EP4012865A1

公开(公告)日：2022-06-15

申请号：EP21209605.1

申请日：2021-11-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  GIORDANO, Antonio ,  PENNISI, Orazio ,  PEDONE, Leonardo ,  FINAZZI, Luca

IPC: H02H3/087

Abstract: An overcurrent (OVC) diagnostic circuit comprises comparator circuitry (200) configured to sense a current through a load (L) and compare the intensity of the current sensed with a comparison threshold which can be set to a first, lower threshold value (OVC_thr_1) and to a second, higher threshold value (OVC_thr_2). Logic circuitry (300) receives from the comparator circuitry (200) a comparison signal having a first value or a second value as a function of whether the current intensity is lower or higher than the comparison threshold (OVC_thr_1, OVC_thr_2). The logic circuitry (300) is configured (302) to set the comparison threshold of the comparator circuitry (200) alternately to the first threshold value (OVC_thr_1) and to the second threshold value (OVC_thr_2) and:
assert a first overcurrent event signal (OVC_1_Fault) in response to the comparison signal having the second value with the comparison threshold set to the first threshold value (OVC_thr_1) and the first value with the comparison threshold set to the second threshold value (OVC_thr_2),
assert a second overcurrent event signal (OVC_2_Fault) in response to the comparison signal having the second value both with the comparison threshold set to the first threshold value (OVC_thr_1) and with the comparison threshold set to the second threshold value (OVC_thr_2).