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    Method and circuit for minimizing glitches in phase locked loops
    1.
    发明公开
    Method and circuit for minimizing glitches in phase locked loops 有权
    Phasenregelkreisen的Verfahren und Schaltung zur Minimierung vonStörsignalen

    公开(公告)号：EP1047196A1

    公开(公告)日：2000-10-25

    申请号：EP99830234.3

    申请日：1999-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magazzu', Antonio ,  Marletta, Benedetto Marco ,  Gramegna, Giuseppe ,  D'Aquila, Alessandro

    IPC: H03L7/089 ,  H03L7/183

    CPC classification number: H03K17/162 ,  H03L7/0891 ,  H03L7/183

    Abstract: The invention relates to a method and a circuit (7) for minimizing glitches in phase-locked loops. The circuit is of the type which comprises an input terminal (EXT) connected to an input of a phase detector (8); a series of a charge pump generator (9), a filter (10) and a voltage controlled oscillator (11) connected downstream of the phase detector (8); and a frequency divider (12) feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector (8).
    The invention provides for the inclusion of a compensation circuit (13) connected between the charge pump generator (9) and the filter (10) to absorb an amount of the charge passed therethrough. This compensation circuit (13) includes a storage element (14) connected in series to a switch (15) which is controlled by a control signal (Cpoff) from the charge pump generator (9).

    Abstract translation: 输入端子（EXT）连接到相位检测器（8）的输入端。 电荷泵发生器（9），滤波器（10）和压控振荡器（11）连接在下游。 分频器（12）反馈连接在振荡器的输出端和检测器的第二输入端之间。 包括由发电机信号控制的存储元件的补偿电路（13）连接在发电机和滤波器之间，吸收一些电荷。 包括用于最小化锁相环中的毛刺产生的方法的独立权利要求。

    High-frequency clipping stage
    3.
    发明公开
    High-frequency clipping stage 审中-公开
    Hochfrequenzbegrenzungsstufe

    公开(公告)号：EP1047194A1

    公开(公告)日：2000-10-25

    申请号：EP99830239.2

    申请日：1999-04-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magazzu', Antonio ,  Pelleriti, Roberto ,  Marletta, Benedetto Marco

    IPC: H03K19/013 ,  H03K5/24 ,  H03F3/30

    CPC classification number: H03F3/3071 ,  H03K5/2418 ,  H03K19/0136

    Abstract: A clipping stage, particularly for high frequencies, which comprises:

    a first power supply line (V CC ) and a second power supply line (V EE );
    a differential input stage which is constituted by a first transistor (Q1) and a second transistor (Q2), is supplied by a first current source (Q4, R4) and is interposed between said first power supply line and said second power supply line;
    a third transistor (Q3) which is connected between said first power supply line and said second power supply line and to said input stage and is supplied with power by a second current source (Q5, R5);
    an output stage which is connected to said input stage and to an output load (R L , C L );
    the particularity of which consists of the fact that the stage further comprises an active load (Q8) which is arranged in parallel to said output load (R L , C L ) and means (C) for driving said active load (Q8) which are suitable to drive the starting of a current pulse from said third transistor (Q3) to said active load (Q8), in order to provide a faster falling front of the output signal of said output stage.

    Abstract translation: 包括由电流源（Q4，R4）提供的两个晶体管（Q1，Q2）的差分输入级连接在两条电源线之间。 连接在线路和输入级之间的第三晶体管（Q3）由第二电流源（Q5，R5）提供。 输出级连接到与驱动（C）的有源负载（Q8）并联的输出负载，以便从第三晶体管启动电流脉冲，从而提供输出信号的更快的下降沿。

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