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1.发明公开Method of calibrating the frequency of an oscillator in a phase locked loop circuit 有权Methode zum Kalibrieren der Frequenz eines Oszillators in einer Phasenregelschleife
公开(公告)号：EP1638207A1
公开(公告)日：2006-03-22
申请号：EP04425685.7
申请日：2004-09-15
Applicant: STMicroelectronics S.r.l.
Inventor： Filocamo, Basilio , Gramegna, Giuseppe
Abstract: A method for calibrating the frequency of an oscillator in a phase-locked loop (PLL) is disclosed. For calibration, the loop is opened upstream the VCO and a fixed control voltage is applied, while the frequency of the VCO is altered in response to a digital control word supplied for band selection. The VCO is (1.) steered to a highest frequency, (2.) to a lowest frequency and (3.) repeatedly to an intermediate frequency dependent upon the previously measured frequencies and the desired target frequency. The resolution of the frequency measurement is increased from step to step.
Abstract translation: 公开了一种用于校准锁相环（PLL）中的振荡器的频率的方法。 为了进行校准，在VCO的上游开环，并且施加固定的控制电压，同时响应于为频带选择提供的数字控制字而改变VCO的频率。 VCO根据先前测量的频率和期望的目标频率（1.）重复转向最高频率（2.）至最低频率和（3.）至中频。 频率测量的分辨率从一步到一步增加。
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2.发明公开
公开(公告)号：EP1551102A1
公开(公告)日：2005-07-06
申请号：EP03425828.5
申请日：2003-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： Gramegna, Giuseppe
Abstract: A device for calibrating the frequency of an oscillator is described. The oscillator (2) has a first and a second input and generates an output frequency (L*S*fo) as a response to a first voltage signal (Vref) applied at the first input. The calibration device (3) is adapted to generate an output digital signal (WD) applied at said second input of the oscillator (2) for calibrating its output frequency (L*S*fo) and it comprises at least one counter (Ti). The counter (Ti) has a first input frequency (fR/2 i-1 ) proportional to a reference frequency (fR) and a second input frequency (S*fo) proportional to the output frequency (L*S*fo) of the oscillator (2). The counter (Ti) counts the time window number (Fi) given by the ratio of the second (S*fo) to the first frequency (fR/2 i-1 ) and the device (3) comprises means (6) adapted to compare said counted time window number (Fi) with a prefixed time window number (Bi). The calibration device (3) is adapted to change the value of the frequency calibration digital signal (WD) if said counted time window number (Fi) is different from said prefixed time window number (Bi) and until it is obtained that said counted time window number (Fi) is equal to said prefixed time window number (Bi).
Abstract translation: 一种用于校准振荡器的频率装置进行说明。 振荡器（2）具有在所述第一输入端施加第一和第二输入，并且产生输出频率的速率（L * S * FO），以第一电压信号（V REF）的响应。 所述校准装置（3）是angepasst在在所述振荡器（2）的第二输入，用于校准其输出频率（L * S * FO）应用输出数字信号（WD）来产生，并且它包括至少一个计数器（Ti）的 ， 处方（Ti）的具有第一输入频率（f R / 2
）正比于参考频率（f R）和第二输入频率（S * FO）成正比的输出频率（L * S * FO） 振荡器的（2）。 处方（Ti）的计数时间窗数（FI）由所述第二（S * FO）的比例提供给所述第一频率（f R / 2 ）和装置（3）包括装置（6） angepasst到比较所述计数的时间窗数（FI）与预先固定的时间窗口号码（BI）。 所述校准装置（3）是angepasst改变频率校准数字信号（WD），如果所述计数的值的时间窗数（FI）是不同于所述前缀的时间窗数（BI）和，直到它获得的所述计数的时间 窗口数（FI）是等于所述前缀时间窗口号码（BI）。 -
3.发明授权
公开(公告)号：EP1638207B1
公开(公告)日：2008-02-20
申请号：EP04425685.7
申请日：2004-09-15
Applicant: STMicroelectronics S.r.l.
Inventor： Filocamo, Basilio , Gramegna, Giuseppe
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公开(公告)号：EP1047196B1
公开(公告)日：2005-07-20
申请号：EP99830234.3
申请日：1999-04-21
Applicant: STMicroelectronics S.r.l.
CPC classification number: H03K17/162 , H03L7/0891 , H03L7/183
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5.发明公开
公开(公告)号：EP1855379A1
公开(公告)日：2007-11-14
申请号：EP06425321.4
申请日：2006-05-12
Applicant: STMicroelectronics S.r.l.
Inventor： Vaiana, Michele , Gramegna, Giuseppe
IPC: H03F1/30
CPC classification number: H03F1/0261 , H03F1/302 , H03F2200/18 , H03F2200/447 , H03F2200/456 , H03F2200/462 , H03F2200/78
Abstract: Precision and reliability of a current limited mode output power control of an RF amplifier is significantly enhanced by sensing the base current of the current controlled output power transistor (BJT or HBT) and comparing it with a certain control current that is normalized by scaling it in function of the current gain (β) of a bipolar junction transistor of similar characteristics of the output power transistor. Fabrication process spread of current gain figures of bipolar junction transistors is effectively compensated. Moreover, by employing a band-gap temperature compensation control current that is eventually β-scaled before comparing it with the sensed base current of the output power transistor, the output power may be effectively controlled and maintained constant over temperature as well as process spread variations.
Abstract translation: 通过检测电流控制输出功率晶体管（BJT或HBT）的基极电流并将其与通过对其进行归一化归一化的特定控制电流进行比较，可显着提高RF放大器电流限制模式输出功率控制的精度和可靠性 具有输出功率晶体管类似特性的双极结型晶体管的电流增益（²）的函数。 双极结型晶体管的电流增益图的制造工艺扩展得到有效的补偿。 此外，通过采用在将其与输出功率晶体管的检测到的基极电流进行比较之前最终“缩放”的带隙温度补偿控制电流，可以有效地控制输出功率并保持恒定的温度以及工艺扩展变化 。
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Patent Agency Ranking6.发明公开High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers 有权Hochgenaue Vorspannungsschaltungfüreine CMOS Kaskodenstufe，insbesonderefürrauscharmeVerstärker
公开(公告)号：EP1081573A1
公开(公告)日：2001-03-07
申请号：EP99830542.9
申请日：1999-08-31
Applicant: STMicroelectronics S.r.l.
Inventor： Gramegna, Giuseppe , D'Aquila, Alessandro , Merletta, B. Marco
CPC classification number: G05F3/205 , H03F1/223 , H03F1/301 , H03F3/45201 , H03F2200/294 , H03F2200/372 , H03F2200/453 , H03F2203/45464 , H03F2203/45696 , H03F2203/45704
Abstract: A novel splitting bias technique is proposed by the invention. The problem of biasing a CMOS cascoded final stage is splitted in sub-problems by using sub-circuits. The inventive idea is that of using two transistor replicas (M1b, M2b) of the MOS transistors included in the cascoded stage (2), two current generators I1 and I2 for biasing such transistor replicas and a circuit block (Xb) which reads out the voltage value Vs(M2b) on one terminal a transistor replica (M2b) of and uses such a value to bias the other transistor replica (M1b).
Two circuit implementations have been used for the circuit block (Xb): a simple voltage amplifier or a folded cascoded amplifier closed in shunt feedback.
Both implementations allows to track the threshold voltages of the cascoded stage transistors, as well as their early and body effects.Abstract translation: 本发明提出了一种新颖的分裂偏置技术。 通过使用子电路将CMOS级联最终级的偏置问题分解成子问题。 本发明的思想是使用包括在级联（2）中的MOS晶体管的两个晶体管复制品（M1b，M2b），用于偏置这种晶体管副本的两个电流发生器I1和I2以及读出 一个晶体管复制（M2b）的一个端子上的电压值Vs（M2b）并且使用这样的值来偏置另一个晶体管复制品（M1b）。 电路块（Xb）已经使用了两个电路实现方式：一个简单的电压放大器或一个折叠式共源放大器，用于分流反馈。 这两种实现允许跟踪级联晶体管的阈值电压以及它们的早期和身体效应。
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7.发明授权
公开(公告)号：EP1551102B1
公开(公告)日：2007-02-14
申请号：EP03425828.5
申请日：2003-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： Gramegna, Giuseppe
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公开(公告)号：EP1517439A1
公开(公告)日：2005-03-23
申请号：EP03425600.8
申请日：2003-09-16
Applicant: STMicroelectronics S.r.l.
Inventor： Gramegna, Giuseppe
CPC classification number: H03F3/45085 , H03F1/083 , H03F1/3211 , H03F2200/294 , H03F2200/372
Abstract: An amplifier comprising at least one amplifier stage (100) is described; the stage (100) includes at least a first transistor (Q1) which has a first input signal (Vi) at a first input terminal and has a first output terminal (Out1) at which a first output amplified signal is present. The first transistor (Q1) comprises a first parasitic capacitive element (Cµ) which is arranged between the first input and output (Out1) terminals and through which a first current (Im1) flows. The stage (100) comprises a device (1) having a second output terminal (Out2) with an output signal having a value equal to but of different sign from the first output signal and it comprises at least one element (2) which is arranged between the first input terminal of the first transistor (Q1) and the second output terminal (Out2) of the device (1) and which is passed through by a second current (Im2) having a value equal to but of different sign from the first current (Im1).
Abstract translation: 描述了包括至少一个放大器级（100）的放大器; 级（100）至少包括第一晶体管（Q1），其在第一输入端具有第一输入信号（Vi），并具有存在第一输出放大信号的第一输出端（Out1）。 第一晶体管（Q1）包括布置在第一输入和输出（Out1）端子之间的第一寄生电容元件（C mu），并且第一电流（Im1）流过该第一寄生电容元件。 级（100）包括具有第二输出端（Out2）的装置（1），其输出信号的值等于但不同于第一输出信号，并且它包括至少一个元件（2），其被布置 在第一晶体管（Q1）的第一输入端和器件（1）的第二输出端（Out2）之间并且通过具有等于但不同符号的值的第二电流（Im2）从第一 电流（Im1）。
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9.发明公开Method and circuit for minimizing glitches in phase locked loops 有权Phasenregelkreisen的Verfahren und Schaltung zur Minimierung vonStörsignalen
公开(公告)号：EP1047196A1
公开(公告)日：2000-10-25
申请号：EP99830234.3
申请日：1999-04-21
Applicant: STMicroelectronics S.r.l.
CPC classification number: H03K17/162 , H03L7/0891 , H03L7/183
Abstract: The invention relates to a method and a circuit (7) for minimizing glitches in phase-locked loops. The circuit is of the type which comprises an input terminal (EXT) connected to an input of a phase detector (8); a series of a charge pump generator (9), a filter (10) and a voltage controlled oscillator (11) connected downstream of the phase detector (8); and a frequency divider (12) feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector (8).
The invention provides for the inclusion of a compensation circuit (13) connected between the charge pump generator (9) and the filter (10) to absorb an amount of the charge passed therethrough. This compensation circuit (13) includes a storage element (14) connected in series to a switch (15) which is controlled by a control signal (Cpoff) from the charge pump generator (9).Abstract translation: 输入端子（EXT）连接到相位检测器（8）的输入端。 电荷泵发生器（9），滤波器（10）和压控振荡器（11）连接在下游。 分频器（12）反馈连接在振荡器的输出端和检测器的第二输入端之间。 包括由发电机信号控制的存储元件的补偿电路（13）连接在发电机和滤波器之间，吸收一些电荷。 包括用于最小化锁相环中的毛刺产生的方法的独立权利要求。
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10.发明授权High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers 有权对于CMOS高精度偏置电路级联阶段，特别是用于低噪声放大器
公开(公告)号：EP1081573B1
公开(公告)日：2003-04-09
申请号：EP99830542.9
申请日：1999-08-31
Applicant: STMicroelectronics S.r.l.
Inventor： Gramegna, Giuseppe , D'Aquila, Alessandro , Merletta, B. Marco
CPC classification number: G05F3/205 , H03F1/223 , H03F1/301 , H03F3/45201 , H03F2200/294 , H03F2200/372 , H03F2200/453 , H03F2203/45464 , H03F2203/45696 , H03F2203/45704
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