公开(公告)号：EP1094608B1

公开(公告)日：2005-12-28

申请号：EP99830657.5

申请日：1999-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Guinea, Jesus ,  Tomasini, Luciano ,  Maggio, Santo

IPC: H03L7/081 ,  H03L7/091

CPC classification number: H03L7/0812 ,  H03L7/091

公开(公告)号：EP1094608A1

公开(公告)日：2001-04-25

申请号：EP99830657.5

申请日：1999-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Guinea, Jesus ,  Tomasini, Luciano ,  Maggio, Santo

IPC: H03L7/081 ,  H03L7/091

CPC classification number: H03L7/0812 ,  H03L7/091

Abstract: A delay-locked loop circuit ("DLL") comprises a delay line (1) with a delay (Δt) which can be varied in a controlled manner in order to delay a periodic input signal (CKin) of period T, and circuit means (2, 7) for controlling the delay line (1) in order to lock the delay (Δt) to the period T.
The delay line (1) supplies to the control circuit means (2, 7) a plurality of periodic signals (CK1-CKN) each delayed relative to the periodic input signal by a respective fraction of the delay (Δt), and the control circuit means (2, 7) comprise sequence-detector circuit means (2) which can periodically detect, in the delayed signals, characteristic sequences of digital values indicative of the delay (Δt) and, in dependence on the type of characteristic sequence, can bring about a reduction or an increase in the delay (Δt) for locking to the period T.

Abstract translation: 延迟锁定环电路（“DLL”）包括具有延迟（DELTA t）的延迟线（1），其可以以受控的方式变化，以便延迟周期T的周期性输入信号（CKin），并且电路 用于控制延迟线（1）以便将延迟（DELTA t）锁定到周期T的装置（2,7）。延迟线（1）向控制电路装置（2,7）供应多个周期 信号（CK1-CKN）各自相对于周期性输入信号延迟相应的延迟分数（DELTA t），并且控制电路装置（2,7）包括顺序检测器电路装置（2） 在延迟信号中，指示延迟（DELTA t）的数字值的特征序列和根据特征序列的类型可以导致锁定到周期T的延迟（DELTA t）的减小或增加 。