公开(公告)号：EP0955576A1

公开(公告)日：1999-11-10

申请号：EP98830278.2

申请日：1998-05-08

Applicant: STMicroelectronics S.r.l.

Inventor： Savo, Pierandrea ,  Zangrandi, Luigi ,  Marcheses, Stefano

IPC: G06F7/50

CPC classification number: G06F7/5095 ,  G06F2207/3884

Abstract: A high-speed digital accumulator with wide dynamic range, the particularity whereof is the fact that it comprises a first adder stage (15), in which an input addend (X) is added to a value of a least significant part (11) of an accumulator at the preceding clock period, and at least one second stage, which comprises incrementer/decrementer means (18) suitable to perform an increment, decrement or identity operation on a most significant part of the accumulator, the incrementer/decrementer means further comprising logic means suitable to trigger an increment, a decrement or an identity of the most significant part on the basis of a decision made on results obtained at the previous clock period.

Abstract translation: 一种具有宽动态范围的高速数字累加器，其特殊性在于它包括第一加法器级（15），其中将输入加数（X）加到最小有效部分（11）的值 在前一时钟周期的累加器和至少一个第二级，其包括适于在累加器的最高有效部分上执行增量，减量或识别操作的递增器/减法器装置（18），所述递增器/减法器装置还包括 逻辑装置适合于根据对在前一个时钟周期获得的结果作出的决定来触发最重要部分的增量，减量或同一性。