公开(公告)号：EP1100125A1

公开(公告)日：2001-05-16

申请号：EP99830699.7

申请日：1999-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Vai, Gianfranco ,  Savo, Pierandrea

IPC: H01L23/544 ,  G06F11/00 ,  G11C17/10

CPC classification number: G11C17/10 ,  G06F11/006 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated device (100) comprising a plurality of conducting layers (115a-115c), each having a first (120ga-120gc) and a second (120va-120vc) power supply contact for providing, respectively, a first and a second binary value, and means for supplying at least one identification bit of a version of the integrated device (100); the integrated device (100) includes, for each identification bit, parity check means (135abi, 135bci) having a plurality of input terminals whose number is equal to the number of conducting layers (115a-115c), and an output terminal, each input terminal being connected to one contact selected from the first (120ga-120gc) and the second (120va-120vc) power supply contacts of a corresponding one of the conducting layers (115a-115c), and the output terminal supplying the corresponding identification bit.

Abstract translation: 集成器件（100）包括导电层（115A-115C）的复数，每个都具有第一（120ga-120gc）和用于提供第二（120VA-120vc）供电接触件，分别为第一和第二二进制值， 和装置，用于提供一个版本的集成设备（100）中的至少一个识别位; 集成器件（100）包括，对于每个识别位，奇偶校验手段（135abi，135bci），其具有输入端子，其数量等于导电层（115A-115C）的数量，和输出端子的复数，每个输入 端子被连接到从第一（120ga-120gc）选择的一个接触，并且相应的所述导电层中的一个（115A-115C）的第二个（120VA-120vc）电源触点，和输出端供给对应的识别位。

公开(公告)号：EP1020990A3

公开(公告)日：2000-08-02

申请号：EP99830379.6

申请日：1999-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

IPC: H03F3/45

CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

Abstract translation: 一种跨导器，包括由一对输入晶体管构成的差分级，一个对所述差分级的输入晶体管的源极进行对流的负反馈电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应输入晶体管的源极和 共同的接地节点具有由串联的一个或多个晶体管构成的电阻性退化线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设定为在三极管 地区。

公开(公告)号：EP0955576B1

公开(公告)日：2003-08-13

申请号：EP98830278.2

申请日：1998-05-08

Applicant: STMicroelectronics S.r.l.

Inventor： Savo, Pierandrea ,  Zangrandi, Luigi ,  Marchese, Stefano

IPC: G06F7/50

CPC classification number: G06F7/5095 ,  G06F2207/3884

公开(公告)号：EP1020990A2

公开(公告)日：2000-07-19

申请号：EP99830379.6

申请日：1999-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

IPC: H03F3/45

CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

Abstract translation: 一种跨导体，包括由一对输入晶体管组成的差分级，与所述差分级的输入晶体管的源极对流的电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应的输入晶体管的源极和 公共接地节点具有由串联的一个或多个晶体管组成的退化电阻线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设计成在三极管中工作 地区。

公开(公告)号：EP0955576A1

公开(公告)日：1999-11-10

申请号：EP98830278.2

申请日：1998-05-08

Applicant: STMicroelectronics S.r.l.

Inventor： Savo, Pierandrea ,  Zangrandi, Luigi ,  Marcheses, Stefano

IPC: G06F7/50

CPC classification number: G06F7/5095 ,  G06F2207/3884

Abstract: A high-speed digital accumulator with wide dynamic range, the particularity whereof is the fact that it comprises a first adder stage (15), in which an input addend (X) is added to a value of a least significant part (11) of an accumulator at the preceding clock period, and at least one second stage, which comprises incrementer/decrementer means (18) suitable to perform an increment, decrement or identity operation on a most significant part of the accumulator, the incrementer/decrementer means further comprising logic means suitable to trigger an increment, a decrement or an identity of the most significant part on the basis of a decision made on results obtained at the previous clock period.

Abstract translation: 一种具有宽动态范围的高速数字累加器，其特殊性在于它包括第一加法器级（15），其中将输入加数（X）加到最小有效部分（11）的值 在前一时钟周期的累加器和至少一个第二级，其包括适于在累加器的最高有效部分上执行增量，减量或识别操作的递增器/减法器装置（18），所述递增器/减法器装置还包括 逻辑装置适合于根据对在前一个时钟周期获得的结果作出的决定来触发最重要部分的增量，减量或同一性。