公开(公告)号：EP1630882A1

公开(公告)日：2006-03-01

申请号：EP04425649.3

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  G11C13/02

CPC classification number: H01L51/0021 ,  H01L51/0595 ,  Y10S977/712 ,  Y10S977/781

Abstract: A hosting structure of nanometric components is described advantageously comprising:

a substrate (1);
n array levels (20, 30, 40) on said substrate (1), with n ≥ 2, arranged consecutively on growing and parallel planes,
each including a plurality of conductive spacers (11, 41) alternated to a plurality of insulating spacers (12, 42) and substantially perpendicular to said substrate (1), with definition between consecutive conductive spacers (11, 41) of at least a gap (13),
conductive spacers of consecutive array levels (20, 30, 40) lying on distinct and parallel planes, said gaps (13) of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate (1) with definition of a plurality of transversal hosting seats (13a, 130a) extended along said direction and suitable for hosting at least a nanometric component.

A nanometric electronic device is also described comprising such a hosting structure and a method for realising it.

公开(公告)号：EP1630127A1

公开(公告)日：2006-03-01

申请号：EP04425647.7

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: B81C1/00 ,  B82B3/00

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  Y10S977/70 ,  Y10S977/701

Abstract: Method for realising a hosting structure of nanomettric elements (A, B) comprising the steps of depositing on an upper surface (12) of a substrate (10), of a first material, a block-seed (15) having at least one side wall (18). Depositing on at least one portion of sad surface (12) and on the block-seed (15) a first layer (20), of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it realising a spacer-seed (22) adjacent to the side wall (18). The method thus providing to repeat n times, with n >= 2, a step comprising a deposition on the substrate (10) of a layer (20, 30) of a predetermined material followed by a selective and anisotropic etching of the layer with realisation of at least one relative spacer (25, 35). This predetermined material being different for each pair of consecutive depositions. The above n steps defining at least one multilayer body (50, 150, 250). The method thus providing the step of selectively etching the multilayer body (50, 150, 250) removing a fraction of the spacers realising at least one plurality of nanometric hosting seats (40), the remaining fraction of the spacers realising contact terminals for a plurality of molecular transistors hosted in said hosting seats (40).

公开(公告)号：EP1741671A1

公开(公告)日：2007-01-10

申请号：EP05425488.3

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco

IPC: B82B3/00 ,  G11C13/02 ,  H01L21/768

CPC classification number: H01L21/76838 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11C2213/81 ,  H01L21/76816 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for realising an electric connection in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components, which comprising the steps of:
a) providing a nanometric circuit architecture comprising a succession (array) (3) of conductive nanowires (2) being substantially parallel to each other and extended along a predetermined direction x;
b) realising, above the succession (3) of nanowires (2), an insulating layer (6);
c) opening, on the insulating layer (6), a window (7) of nanometric width b extended along a direction inclined of an angle α with respect to the extension direction x of the nanowires (2) so as to substantially cross the whole succession (3) of nanowires (2), with exposure of a succession (11) of exposed portions (10) of the nanowires (2), one for each nanowire;
d) realising, above the insulating layer (6), a plurality of conductive dies (4) extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies (4) overlapping in correspondence with said window (7) onto a respective exposed portion (10) of a nanowire (2) with obtainment of a plurality of contacts (5) realising said electric connection.

Abstract translation: 本发明涉及一种用于纳米电路结构和标准电子部件，这包括以下步骤之间在一个半导体电子器件的电连接的真实伊辛的方法：（a）提供纳米电路结构，其包括一个连续阵列）（3）的 导电纳米线（2）基本上彼此平行并沿着方向X个预定延长; b）中实伊辛，继承上述（3）纳米线（2），（绝缘层6）; c）中的开口，在绝缘层（6）上，窗口（7）纳米宽度b沿着倾斜的角度为±相对于纳米线的延伸方向x的方向延伸的（2），以便基本上横穿整个 纳米线（2），与所述纳米线（2），一个用于每个纳米线的暴露部分（10）的连续（11）的曝光的连续（3）; D）实伊辛，绝缘层上述（6），导电的多元性这个（4）沿一个方向y大致正交的x方向延伸，并朝向所述标准的电子元件，各自寻求解决了这个（4）对应于重叠 所述窗口（7）到纳米线（2）的带触点（5）的多个获取一个respectivement暴露部分（10）实现所述电连接。

公开(公告)号：EP1630881A1

公开(公告)日：2006-03-01

申请号：EP04425648.5

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  H01L51/40 ,  G11C13/02

CPC classification number: H01L51/0021 ,  G11C2213/77 ,  H01L27/285 ,  H01L51/0595 ,  Y10S257/90 ,  Y10S977/712 ,  Y10S977/72 ,  Y10S977/722 ,  Y10S977/723

Abstract: A hosting structure of nanometric components is described comprising
a substrate (1),
a first multispacer level (70) comprising a first plurality of spacers (5a) including first conductive spacers (5a) parallel to each other, and
at least a second multispacer level (71) realised above said first multispacer level (70) and comprising a second plurality of spacers (7) arranged transversally to said first plurality of spacers (5a) and including at least a lower discontinuous insulating layer (8) and an upper layer, including in turn second conductive spacers (11a).
In particular, each pair of spacers (7) of the second multispacer level (71) defines with a spacer (5a) of the first multispacer level (70) a plurality of nanometric hosting seats (15) having at least a first and a second conduction terminal (13a, 13b) realised by portions of the first conductive spacers (5a) and of the second conductive spacers (11a) faced in the hosting seats (15).
A method for manufacturing such a structure is also described.

公开(公告)号：EP1630882B1

公开(公告)日：2012-05-02

申请号：EP04425649.3

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  G11C13/02 ,  B82Y10/00

CPC classification number: H01L51/0021 ,  H01L51/0595 ,  Y10S977/712 ,  Y10S977/781

公开(公告)号：EP1630127B1

公开(公告)日：2008-09-10

申请号：EP04425647.7

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: B81C1/00 ,  G03F7/00 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  Y10S977/70 ,  Y10S977/701

公开(公告)号：EP1528039A1

公开(公告)日：2005-05-04

申请号：EP04025635.6

申请日：2004-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Scaldaferri, Rossana ,  Napolitano, Teresa ,  Casuscelli, Valeria ,  Occhipinti, Luigi

IPC: B82B3/00 ,  B82B1/00 ,  H01L49/00 ,  H01L29/76

CPC classification number: B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L49/006 ,  Y10S438/969

Abstract: The present invention relates to a method for manufacturing a single electron device (80) by electro-migration of nanoclusters (52). The inventive method comprises the steps of:

patterning a substrate (10, 40);
preparing metallic passivated nanoclusters (52);
forcing the metallic passivated nanoclusters (52) to assembly over the patterned substrate (10) under control of a non homogeneous electric field.

The invention also relates to a single electron device comprising a quantum dot as single electron component.

公开(公告)号：EP1772773A1

公开(公告)日：2007-04-11

申请号：EP05425698.7

申请日：2005-10-06

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco

IPC: G03F7/00 ,  H01L27/10

CPC classification number: H01L21/32139 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017 ,  H01L27/10 ,  Y10S438/946 ,  Y10S438/947 ,  Y10S977/887 ,  Y10S977/888

Abstract: The present invention relates to a method for realising a multispacer structure (1) comprising an array (3) of spacers (2) having same height, comprising the steps of:
a) realising, on a substrate (A), a sacrificial layer (4) of a predetermined first material;
b) realising, on the sacrificial layer (4), a sequence of mask spacers (5, 6) obtained by means of S n PT, which are alternatively obtained in at least two different materials;
c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer (4);
d) chemically and/or anisotropically etching the predetermined first material with selective removal of the exposed portions of the sacrificial layer (4);
e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure (1).

Abstract translation: 本发明涉及一种方法，用于实伊辛（1）包括阵列（3）的间隔件（2）具有相同的高度，其包括以下步骤的一个multispacer结构：1）真实伊辛，在基板（A），一个牺牲层（ 4）在预定的第一材料制成; b）中实伊辛，牺牲层（4），掩模间隔物的（一个序列5上，6）由S n中PT，其是在至少两个不同的材料可替代地获得来获得; c）中化学蚀刻以选择性地去除该蚀刻材料和牺牲层的部分曝光的掩模间隔物的两种不同的材料中的一个（4）; D）化学和/或各向异性蚀刻以选择性地去除所述牺牲层的暴露部分的预定第一材料（4）; E）化学蚀刻以选择性地去除multispacer结构（1）的这个被蚀刻材料和取得的掩模间隔物的两种不同的材料中的另一个。

公开(公告)号：EP1742226A1

公开(公告)日：2007-01-10

申请号：EP05425489.1

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  Mascolo, Danilo

IPC: G11C13/02 ,  H01L21/768 ,  B82B3/00

CPC classification number: H01L21/76816 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/70916 ,  G11C2213/81 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: The invention relates to a method for realising an electric connection in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components, comprising the steps of:
a) providing, above a semiconductor substrate (A), a seed (6) having at least a notched wall (7) substantially perpendicular to the substrate (A), which is crossed by n recesses placed at a distance bo from one another and having depth a n ≥(n-1)t sp +a 0 and width b n =2t si +2(n-1)t sp ;
b) realising, from the seed (6) by means of S n PT, n conductive nanowires (2) of thickness t si alternated with insulating nanowires (3) of thickness (t sp -t si ) wherein t sp is the width of a pair of consecutive conductive (2) and insulating (3) nanowires, so as to obtain, at each realisation of a conductive nanowire (2) of a given order, the filling or the completion of the filling of a recess (8) of the same order by means of a respective elbow-like portion (2a) of the conductive nanowire (2), and the partial filling together with the conductive (2) and insulating (3) nanowires of lower order already realised, of the recesses (8) of greater order by means of respective portions with notched profile (2b; 3b) and formation of the nanometric circuit architecture.
c) realising, above the nanometric circuit architecture, an insulating layer (9);
d) opening, on the insulating layer, n windows (10), each window (10) being open essentially in correspondence with a respective recess (8), with exposure of at least part of an elbow-like portion (2a) of a conductive nanowire (2) present in said recess (8).
e) realising, above the insulating layer (9), n conductive dies (4) addressed towards the standard electronic components, each die (4) overlapping in correspondence with a respective window (10) to a respective exposed part of the elbow-like portion (2a) of a conductive nanowire (2) with obtainment of n contacts (5) realising the electric connection.

Abstract translation: 本发明涉及一种用于纳米电路结构和标准电子部件之间的半导体电子器件的电连接的真实伊辛的方法，包括以下步骤：a）提供，上述的半导体基板（A），具有在种子（6） 至少一个凹口的壁（7）基本垂直于所述基体（A），这是通过在彼此的距离柏摆放着n凹槽交叉，并具有‰¥（N-1）T SP的深度+ a 0和宽度BN = 2吨SI 2（N-1）T SP; b）中实伊辛，从种子（6）由S n中PT的手段，N导电纳米线（2）厚度t SI的交替有绝缘纳米线（3）厚度的（T SP -t SI）worin吨SP是的宽度 一对连续的导电的（2）和绝缘（3）纳米线，以获得在给定顺序的导电纳米线（2）的每个实现，填充或一个凹部的填充完成（8）的 相同的顺序由导电纳米线（2）的一个respectivement肘状部（2a）的平均值，并与导电的（2）和部分填充一起绝缘（3）较低阶的纳米线已经实现了凹部，（ 通过respectivement部的方式与凹口的轮廓（图2b，3b）的与形成所述纳米电路结构的更大的顺序的8）。 c）中实伊辛，所述纳米电路结构的上方，（在绝缘层9）; D）开口，在绝缘层上，N个窗口（10），每个窗口（10）被打开基本上与respectivement凹部（8）对应，具有一个肘状部（2a）的至少一部分的曝光 导电纳米线（2）存在于所述凹部（8）。 E）实伊辛，绝缘层（9）的上方，N导电此（4）朝向所述标准电子元件寻址，每个（4）对应于一个respectivement窗口（10），以一个respectivement重叠露出的一部分肘状 在导电性纳米线（2）中n触头（5）实伊辛的电连接的获得的部分（2a）中。