公开(公告)号：EP1630882A1

公开(公告)日：2006-03-01

申请号：EP04425649.3

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  G11C13/02

CPC classification number: H01L51/0021 ,  H01L51/0595 ,  Y10S977/712 ,  Y10S977/781

Abstract: A hosting structure of nanometric components is described advantageously comprising:

a substrate (1);
n array levels (20, 30, 40) on said substrate (1), with n ≥ 2, arranged consecutively on growing and parallel planes,
each including a plurality of conductive spacers (11, 41) alternated to a plurality of insulating spacers (12, 42) and substantially perpendicular to said substrate (1), with definition between consecutive conductive spacers (11, 41) of at least a gap (13),
conductive spacers of consecutive array levels (20, 30, 40) lying on distinct and parallel planes, said gaps (13) of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate (1) with definition of a plurality of transversal hosting seats (13a, 130a) extended along said direction and suitable for hosting at least a nanometric component.

A nanometric electronic device is also described comprising such a hosting structure and a method for realising it.

公开(公告)号：EP1630127A1

公开(公告)日：2006-03-01

申请号：EP04425647.7

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: B81C1/00 ,  B82B3/00

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  Y10S977/70 ,  Y10S977/701

Abstract: Method for realising a hosting structure of nanomettric elements (A, B) comprising the steps of depositing on an upper surface (12) of a substrate (10), of a first material, a block-seed (15) having at least one side wall (18). Depositing on at least one portion of sad surface (12) and on the block-seed (15) a first layer (20), of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it realising a spacer-seed (22) adjacent to the side wall (18). The method thus providing to repeat n times, with n >= 2, a step comprising a deposition on the substrate (10) of a layer (20, 30) of a predetermined material followed by a selective and anisotropic etching of the layer with realisation of at least one relative spacer (25, 35). This predetermined material being different for each pair of consecutive depositions. The above n steps defining at least one multilayer body (50, 150, 250). The method thus providing the step of selectively etching the multilayer body (50, 150, 250) removing a fraction of the spacers realising at least one plurality of nanometric hosting seats (40), the remaining fraction of the spacers realising contact terminals for a plurality of molecular transistors hosted in said hosting seats (40).

公开(公告)号：EP0889505B1

公开(公告)日：2005-06-08

申请号：EP97830335.2

申请日：1997-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Queirolo, Giuseppe ,  Ottaviani, Giampiero ,  Cerofolini, Gianfranco

IPC: H01L21/306

CPC classification number: H01L21/306 ,  H01L21/3043

公开(公告)号：EP1630882B1

公开(公告)日：2012-05-02

申请号：EP04425649.3

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  G11C13/02 ,  B82Y10/00

CPC classification number: H01L51/0021 ,  H01L51/0595 ,  Y10S977/712 ,  Y10S977/781

公开(公告)号：EP1630127B1

公开(公告)日：2008-09-10

申请号：EP04425647.7

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: B81C1/00 ,  G03F7/00 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  Y10S977/70 ,  Y10S977/701

公开(公告)号：EP1278234A3

公开(公告)日：2004-04-28

申请号：EP01127923.9

申请日：2001-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  Ferla, Giuseppe

IPC: H01L21/28 ,  H01L29/51 ,  H01L51/20

CPC classification number: H01L21/28167 ,  H01L29/51

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer (3) formed between two silicon plates (1,2), and wherein the silicon plates (1,2) overhang the oxide layer (3) all around to define an undercut (5) having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates (1,2) to have different functional groups (6,7) provided in the undercut (5) from those in the remainder of the surfaces; and selectively reacting the functional groups (6,7) provided in the undercut (5) with an organic molecule (8) having a reversibly reducible center and a molecular length substantially equal to the width of the undercut (5), thereby to establish a covalent bond to each end of the organic molecule (8).

公开(公告)号：EP1741671A1

公开(公告)日：2007-01-10

申请号：EP05425488.3

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco

IPC: B82B3/00 ,  G11C13/02 ,  H01L21/768

CPC classification number: H01L21/76838 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11C2213/81 ,  H01L21/76816 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for realising an electric connection in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components, which comprising the steps of:
a) providing a nanometric circuit architecture comprising a succession (array) (3) of conductive nanowires (2) being substantially parallel to each other and extended along a predetermined direction x;
b) realising, above the succession (3) of nanowires (2), an insulating layer (6);
c) opening, on the insulating layer (6), a window (7) of nanometric width b extended along a direction inclined of an angle α with respect to the extension direction x of the nanowires (2) so as to substantially cross the whole succession (3) of nanowires (2), with exposure of a succession (11) of exposed portions (10) of the nanowires (2), one for each nanowire;
d) realising, above the insulating layer (6), a plurality of conductive dies (4) extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies (4) overlapping in correspondence with said window (7) onto a respective exposed portion (10) of a nanowire (2) with obtainment of a plurality of contacts (5) realising said electric connection.

Abstract translation: 本发明涉及一种用于纳米电路结构和标准电子部件，这包括以下步骤之间在一个半导体电子器件的电连接的真实伊辛的方法：（a）提供纳米电路结构，其包括一个连续阵列）（3）的 导电纳米线（2）基本上彼此平行并沿着方向X个预定延长; b）中实伊辛，继承上述（3）纳米线（2），（绝缘层6）; c）中的开口，在绝缘层（6）上，窗口（7）纳米宽度b沿着倾斜的角度为±相对于纳米线的延伸方向x的方向延伸的（2），以便基本上横穿整个 纳米线（2），与所述纳米线（2），一个用于每个纳米线的暴露部分（10）的连续（11）的曝光的连续（3）; D）实伊辛，绝缘层上述（6），导电的多元性这个（4）沿一个方向y大致正交的x方向延伸，并朝向所述标准的电子元件，各自寻求解决了这个（4）对应于重叠 所述窗口（7）到纳米线（2）的带触点（5）的多个获取一个respectivement暴露部分（10）实现所述电连接。

公开(公告)号：EP1630881A1

公开(公告)日：2006-03-01

申请号：EP04425648.5

申请日：2004-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  H01L51/40 ,  G11C13/02

CPC classification number: H01L51/0021 ,  G11C2213/77 ,  H01L27/285 ,  H01L51/0595 ,  Y10S257/90 ,  Y10S977/712 ,  Y10S977/72 ,  Y10S977/722 ,  Y10S977/723

Abstract: A hosting structure of nanometric components is described comprising
a substrate (1),
a first multispacer level (70) comprising a first plurality of spacers (5a) including first conductive spacers (5a) parallel to each other, and
at least a second multispacer level (71) realised above said first multispacer level (70) and comprising a second plurality of spacers (7) arranged transversally to said first plurality of spacers (5a) and including at least a lower discontinuous insulating layer (8) and an upper layer, including in turn second conductive spacers (11a).
In particular, each pair of spacers (7) of the second multispacer level (71) defines with a spacer (5a) of the first multispacer level (70) a plurality of nanometric hosting seats (15) having at least a first and a second conduction terminal (13a, 13b) realised by portions of the first conductive spacers (5a) and of the second conductive spacers (11a) faced in the hosting seats (15).
A method for manufacturing such a structure is also described.

公开(公告)号：EP0875905B1

公开(公告)日：2001-06-27

申请号：EP97830194.3

申请日：1997-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  De Santi, Giorgio ,  Crisenza, Giuseppe

IPC: H01B3/30 ,  C08F292/00 ,  H01L23/532

CPC classification number: H01B3/30 ,  C08F292/00 ,  H01L23/5329 ,  H01L2924/0002 ,  Y02P20/544 ,  H01L2924/00

公开(公告)号：EP0889505A1

公开(公告)日：1999-01-07

申请号：EP97830335.2

申请日：1997-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Queirolo, Giuseppe ,  Ottaviani, Giampiero ,  Cerofolini, Gianfranco

IPC: H01L21/306

CPC classification number: H01L21/306 ,  H01L21/3043

Abstract: A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines the etch area on the surface of a monocrystallin silicon wafer eventually covered by a thin layer of oxide; implanting ions with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region; and heating the implanted wafer causing dislodgment and expulsion of the amorphized portion in correspondence of the interface with the adjacent crystal lattice of the silicon.

Abstract translation: 在由掩模限定的区域中切割硅单晶中的沟槽的工艺包括形成掩模，其限定最终被薄层氧化物覆盖的单晶硅晶片的表面上的蚀刻区域; 以足够的动能注入离子并使剂量足以将硅非晶硅降低到限定区域内的预定深度，同时保持晶片的温度足够低以防止在硅中产生的点缺陷的弛豫和注入离子的扩散 在与非晶化区相邻的硅的晶格中; 并且加热植入的晶片，导致对应于与硅的相邻晶格的界面的非晶化部分的移动和排出。