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    Class-D amplifier with enhanced bandwidth
    1.
    发明公开
    Class-D amplifier with enhanced bandwidth 有权
    Klasse DVerstärkermit hoher Bandbreite

    公开(公告)号：EP1049247A1

    公开(公告)日：2000-11-02

    申请号：EP99830247.5

    申请日：1999-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Masini, Marco ,  Franchini, Luigi ,  Labbe, Eric

    IPC: H03F3/217

    CPC classification number: H03F3/217

    Abstract: A class-D amplifier comprising an input integrating stage (Op-Amp, R1, C), a modulating stage (PWM) of the integrated input signal output by said integrating stage, using as a carrier an alternate waveform ( Vtr ) of a frequency ( fsw ), sufficiently higher than the frequency band of the analog input signal, outputting a digital signal switching between a positive voltage (+ Vcc ) and a negative voltage ( -Vcc ), and whose average value ( Vo ) represents an amplified replica of the input analog signal, an output power stage (BUFFER), producing an output digital signal ( Vout ), a feedback line constituted by a resistor ( R2 ) connected between the output of said output power stage (BUFFER) and an input node of an operational amplifier ( Op-Amp ) constituting said integrating stage, and a low pass filter reconstructing an output analog signal ( V o), further comprises a delay stage (DELAY Td ), functionally coupled in the direct path of propagation of said digital signal from the output of said PWM stage to an input of said output power stage (BUFFER), delaying said digital signal by a delay ( Td ) whose value is defined in function of a desired broadening of the bandwidth and in consideration of the corresponding restriction of the range of variation of the duty-cycle of the output digital signal.

    Abstract translation: 一种D类放大器，包括输入积分级（Op-Amp，R1，C），由所述积分级输出的积分输入信号的调制级（PWM），使用频率的交替波形（Vtr）作为载波 （fsw），足够高于模拟输入信号的频带，输出在正电压（+ Vcc）和负电压（-Vcc）之间切换的数字信号，其平均值（Vo）表示放大的副本 输出模拟信号，输出功率级（BUFFER），产生输出数字信号（Vout）的反馈线，由连接在所述输出功率级（BUFFER）的输出端和输出节点之间的电阻器（R2）构成的反馈线 构成所述积分级的运算放大器（Op-Amp）和重构输出模拟信号（Vo）的低通滤波器还包括延迟级（DELAY Td），功能上耦合在所述数字信号的传播的直接路径中 所述PWM级的输出 到所述输出功率级（BUFFER）的输入端，将所述数字信号延迟延迟（Td），延迟（Td）的值被定义为期望的带宽宽度的功能，并且考虑到占空比的变化范围的相应限制 - 输出数字信号的循环。

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    5.
    发明公开
    "Constant duty-cycle limiting of analog input signal swing in a class-D amplifier" 有权
    限幅器的模拟Eingangssignalhub在一个D类放大器具有恒定占空比

    公开(公告)号：EP1049248A1

    公开(公告)日：2000-11-02

    申请号：EP99830248.3

    申请日：1999-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Masini, Marco ,  Tavazzani, Claudio

    IPC: H03F3/217 ,  H03G11/00 ,  H03G11/04

    CPC classification number: H03G11/002 ,  H03F3/217 ,  H03F2200/351 ,  H03F2200/66 ,  H03G11/04

    Abstract: A way of establishing a constant limit duty-cycle, substantially independent from fabrication process spread, temperature, etc., and to guarantee an optimal functioning of the final stage of the amplifier for all working conditions consists in detecting the equivalent values of the voltages to which the output signal of the amplifier switches (or pseudo supplies): VDD' and -VDD", respectively, and in making the limiting stage of the voltage swing of analog input signal utilize such pseudo supply values VDD' and -VDD" as respective reference values in limiting the voltage excursion of the analog signal VL output by the input limiting stage to a pre-defined fraction α

    Abstract translation: 建立恒定占空比限制的，基本上独立于制造过程传播，温度等，并保证该放大器的最后一级的最佳状态的运行的所有工作条件besteht在检测的电压的等效值的一种方式 其中放大器的开关（或伪用品）的输出信号：VDD“和-V DD”，分别与在使模拟输入信号的电压摆幅的限制性阶段利用求伪供给值VDD”和-V DD“作为respectivement 在由输入限制阶段求基准值，而不是使用作为基准的实际供给电压值VDD和-VDD的预定义分数的α<1的限制模拟信号VL输出的电压偏移参考值作为常见的做 ，

    PWM bridge amplifier with input network configurable for analog or digital input not needing a triangular wave generator
    8.
    发明公开
    PWM bridge amplifier with input network configurable for analog or digital input not needing a triangular wave generator 有权
    脉宽调制桥式放大器具有可配置输入网络为模拟或数字输入不使用三角波发生器

    公开(公告)号：EP1001526A1

    公开(公告)日：2000-05-17

    申请号：EP98830685.8

    申请日：1998-11-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Botti, Edoardo ,  Grosso, Antonio ,  Masini, Marco

    IPC: H03F3/217

    CPC classification number: H03F3/2173

    Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output, comprises two identical amplifying modules (1, 2), one (1) for the amplifying channel relative to the direct or positive PWM output (Vo-If+) and the other (2) for the amplifying channel relative to the inverted or negative PWM output (Vo-If+). Each modules includes a switching output operational amplifier (O1), having a voltage mode noninverting input (In+), a current mode inverting input (In-) and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform, a logic inverter or a cascade of logic inverters (C1) coupled in cascade to the output of the integrator (O1, LOOP FILTER) and outputting a logic PWM signal, an output power stage (P1) converting the logic PWM signal output by said inverter or cascade of logic inverters (C1) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor (Rf) connecting the output of power stage (P1) to the inverting input (In-) of said operational amplifier (O1).

    Abstract translation: 具有在输入网络配置为标准PWM数字输入信号，相移PWM数字输入信号或模拟输入信号，并为标准PWM输出或相移PWM输出，A低频PWM输出桥式放大器包括两个相同的放大模块（1,2） 中，一个（1）用于相对于所述直接或正PWM输出端（Vo-如果+）和放大通道的另一个（2），用于相对于所述倒置的或负的PWM输出端（Vo-如果+）放大通道。 每个模块包括一个开关输出的运算放大器（01），具有电压模式的同相输入端（IN +），电流模式反相输入端（IN）和一个环路滤波器实现一个单个或多个斜率积分器输出廷的大致三角形的波形的信号 ，逻辑反相器或级联耦合到积分器的输出逻辑反相器（C1）（O1，环路滤波器）和输出廷逻辑PWM信号，以输出功率级（P1）由所述逻辑PWM信号输出转换的级联 逆变器或在PWM信号逻辑的级联，所述电路的两个电源轨的电势之间切换，和反馈电阻的反相器（C1）（RF）功率级（P1）的输出连接到反相输入端（IN- ）所述运算放大器的（O1）。

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