Analog-digital converter with single-ended input
    2.
    发明公开
    Analog-digital converter with single-ended input 有权
    模拟数字播放器Eintakteingang

    公开(公告)号:EP1039642A1

    公开(公告)日:2000-09-27

    申请号:EP99830170.9

    申请日:1999-03-24

    CPC classification number: H03M1/068 H03M1/0845 H03M1/468 H03M1/804

    Abstract: A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).

    Abstract translation: 根据二进制码加权的采样电容器的集合(Array_SAR)通过电容Vcm-Vin / 2的电容等于集电容(Array_SAR)的电容的第一电容单元(Array_Vin)来充电 。 通过SAR处理,通过比较器(13')和操作与电容器相关联的开关(SW1'-SW6')的逻辑单元(14')进行转换。 开关的最终位置被加载到提供数字输出信号(Nout)的寄存器(15')中。 为了防止电源和参考电位源的任何干扰影响转换精度,提供了两个另外的电容单元(Array_-Vref)和(Array_GND),具有与第一个电容单元相同的电容,这些使它 可能以共模显示比较器(13')输入端的所有干扰,因此对输出(OutCmp)没有任何影响。

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