Abstract:
A single-ended or differential single-stage or multi-stage sigma-delta analog-to-digital converter comprises at least a switched-capacitor integrator having a switched-capacitor structure, to an input of which a signal to be sampled is applied, and an amplifier in cascade thereto, and has circuit means coupled to the amplifier for feeding an analog dither signal to a virtual ground node of the amplifier.
Abstract:
The buffer has an output stage (10) formed by two complementary MOS transistors (MPOUT, MNOUT) connected so as to operate in phase opposition between the supply terminals (VDD, earth) and two driver stages (14 and 15) having the input (IN) in common. Each driver stage (14, 15) has a first branch comprising a current-generator (MN4, MP4) connected between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a supply terminal (earth, VDD) and an electronic switch (MP1, MN1) controlled by the input (IN) and connected between the same gate electrode and the other supply terminal (VDD, earth), and a second branch which comprises, connected in series, a transistor connected as a diode (MP3, MN3) and an electronic switch (MP2, MN2) controlled by the output (OUT), and is arranged between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a respective supply terminal (VDD, earth). The buffer can control a load (13) with a constant switching current, is simple in structure, and occupies a small area.
Abstract:
The drawbacks of the use of embedded digital microphones in electronic apparatuses is overcome by a digital microphone destined to be embedded in the apparatus that contemplates the presence of an auxiliary line-in terminal or terminals in the packaged digital microphone device, to which a remote analog microphone (MIC2) may be connected. The result is that the use of an external (remote) analog microphone (MIC2) does not require a dedicated additional analog-to-digital converter. Such a line-in function may even be duplicated even for more than one external analog microphone.
Abstract:
A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).