Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter
    1.
    发明公开
    Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter 有权
    一种用于在最后Integrateurs的输出的Σ-Δ转换器和相关联的换能器增加的抖动信号的方法

    公开(公告)号:EP1727287A1

    公开(公告)日:2006-11-29

    申请号:EP05425374.5

    申请日:2005-05-27

    CPC classification number: H03M3/332 H03M3/424 H03M3/454

    Abstract: A single-ended or differential single-stage or multi-stage sigma-delta analog-to-digital converter comprises at least a switched-capacitor integrator having a switched-capacitor structure, to an input of which a signal to be sampled is applied, and an amplifier in cascade thereto, and has circuit means coupled to the amplifier for feeding an analog dither signal to a virtual ground node of the amplifier.

    Abstract translation: 单端或差分单级或多级Σ-Δ模拟到数字转换器包括具有至少一个开关电容器积分器的开关电容器结构,在其中的输入信号被采样被施加 并在级联放大器于此,并且电路装置,耦合到所述放大器用于馈送到模拟抖动信号到所述放大器的虚拟接地节点。

    An output buffer with constant switching current
    2.
    发明公开
    An output buffer with constant switching current 有权
    Ausgangspuffer mit Konstantschaltstrom

    公开(公告)号:EP1217744A1

    公开(公告)日:2002-06-26

    申请号:EP00830836.3

    申请日:2000-12-21

    CPC classification number: G11C7/1051 H03K19/00361

    Abstract: The buffer has an output stage (10) formed by two complementary MOS transistors (MPOUT, MNOUT) connected so as to operate in phase opposition between the supply terminals (VDD, earth) and two driver stages (14 and 15) having the input (IN) in common. Each driver stage (14, 15) has a first branch comprising a current-generator (MN4, MP4) connected between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a supply terminal (earth, VDD) and an electronic switch (MP1, MN1) controlled by the input (IN) and connected between the same gate electrode and the other supply terminal (VDD, earth), and a second branch which comprises, connected in series, a transistor connected as a diode (MP3, MN3) and an electronic switch (MP2, MN2) controlled by the output (OUT), and is arranged between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a respective supply terminal (VDD, earth). The buffer can control a load (13) with a constant switching current, is simple in structure, and occupies a small area.

    Abstract translation: 缓冲器具有由两个互补MOS晶体管(MPOUT,MNOUT)形成的输出级(10),以在电源端子(VDD,接地)和具有输入端的两个驱动器级(14和15)之间相对操作, IN)的共同点。 每个驱动器级(14,15)具有第一分支,包括连接在待驱动晶体管(MPOUT,MNOUT)的栅电极和电源端(地,VDD)之间的电流发生器(MN4,MP4)和电子 开关(MP1,MN1)由输入(IN)控制并连接在同一个栅极和另一个电源端子(VDD,接地)之间,第二个分支包括串联连接为二极管的晶体管(MP3 ,MN3)和由输出(OUT)控制的电子开关(MP2,MN2),并且被布置在待驱动晶体管(MPOUT,MNOUT)的栅电极和相应的电源端子(VDD,接地)之间。 缓冲器可以用恒定的开关电流控制负载(13),结构简单,占用面积小。

    Packaged digital microphone device with auxiliary line-in function
    4.
    发明公开
    Packaged digital microphone device with auxiliary line-in function 审中-公开
    数码相机Mikrofon mitzusätzlicherEingangsfunktion

    公开(公告)号:EP1565034A1

    公开(公告)日:2005-08-17

    申请号:EP04425098.3

    申请日:2004-02-16

    CPC classification number: H04R1/005 H04R1/04 H04R19/04

    Abstract: The drawbacks of the use of embedded digital microphones in electronic apparatuses is overcome by a digital microphone destined to be embedded in the apparatus that contemplates the presence of an auxiliary line-in terminal or terminals in the packaged digital microphone device, to which a remote analog microphone (MIC2) may be connected.
    The result is that the use of an external (remote) analog microphone (MIC2) does not require a dedicated additional analog-to-digital converter. Such a line-in function may even be duplicated even for more than one external analog microphone.

    Abstract translation: 在电子设备中使用嵌入式数字麦克风的缺点是通过旨在嵌入在设备中的数字麦克风克服,该数字麦克风预期在打包的数字麦克风设备中存在辅助线路输入终端或终端,远程模拟 麦克风(MIC2)可能被连接。 结果是使用外部(远程)模拟麦克风(MIC2)不需要专用的附加模数转换器。 即使对于多于一个的外部模拟麦克风也可能会复制这样的线路输入功能。

    Analog-digital converter with single-ended input
    8.
    发明公开
    Analog-digital converter with single-ended input 有权
    模拟数字播放器Eintakteingang

    公开(公告)号:EP1039642A1

    公开(公告)日:2000-09-27

    申请号:EP99830170.9

    申请日:1999-03-24

    CPC classification number: H03M1/068 H03M1/0845 H03M1/468 H03M1/804

    Abstract: A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).

    Abstract translation: 根据二进制码加权的采样电容器的集合(Array_SAR)通过电容Vcm-Vin / 2的电容等于集电容(Array_SAR)的电容的第一电容单元(Array_Vin)来充电 。 通过SAR处理,通过比较器(13')和操作与电容器相关联的开关(SW1'-SW6')的逻辑单元(14')进行转换。 开关的最终位置被加载到提供数字输出信号(Nout)的寄存器(15')中。 为了防止电源和参考电位源的任何干扰影响转换精度,提供了两个另外的电容单元(Array_-Vref)和(Array_GND),具有与第一个电容单元相同的电容,这些使它 可能以共模显示比较器(13')输入端的所有干扰,因此对输出(OutCmp)没有任何影响。

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