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    High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers
    1.
    发明公开
    High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers 有权
    Hochgenaue Vorspannungsschaltungfüreine CMOS Kaskodenstufe，insbesonderefürrauscharmeVerstärker

    公开(公告)号：EP1081573A1

    公开(公告)日：2001-03-07

    申请号：EP99830542.9

    申请日：1999-08-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gramegna, Giuseppe ,  D'Aquila, Alessandro ,  Merletta, B. Marco

    IPC: G05F3/24 ,  H03F1/22

    CPC classification number: G05F3/205 ,  H03F1/223 ,  H03F1/301 ,  H03F3/45201 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/453 ,  H03F2203/45464 ,  H03F2203/45696 ,  H03F2203/45704

    Abstract: A novel splitting bias technique is proposed by the invention. The problem of biasing a CMOS cascoded final stage is splitted in sub-problems by using sub-circuits. The inventive idea is that of using two transistor replicas (M1b, M2b) of the MOS transistors included in the cascoded stage (2), two current generators I1 and I2 for biasing such transistor replicas and a circuit block (Xb) which reads out the voltage value Vs(M2b) on one terminal a transistor replica (M2b) of and uses such a value to bias the other transistor replica (M1b).
    Two circuit implementations have been used for the circuit block (Xb): a simple voltage amplifier or a folded cascoded amplifier closed in shunt feedback.
    Both implementations allows to track the threshold voltages of the cascoded stage transistors, as well as their early and body effects.

    Abstract translation: 本发明提出了一种新颖的分裂偏置技术。 通过使用子电路将CMOS级联最终级的偏置问题分解成子问题。 本发明的思想是使用包括在级联（2）中的MOS晶体管的两个晶体管复制品（M1b，M2b），用于偏置这种晶体管副本的两个电流发生器I1和I2以及读出 一个晶体管复制（M2b）的一个端子上的电压值Vs（M2b）并且使用这样的值来偏置另一个晶体管复制品（M1b）。 电路块（Xb）已经使用了两个电路实现方式：一个简单的电压放大器或一个折叠式共源放大器，用于分流反馈。 这两种实现允许跟踪级联晶体管的阈值电压以及它们的早期和身体效应。

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