公开(公告)号：EP1439468A3

公开(公告)日：2004-09-08

申请号：EP03079150.3

申请日：2003-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F13/40

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: There is described a method that makes it possible to transmit n binary signals through a bus of m leads, where m

Abstract translation: 描述了一种方法，该方法能够通过在第二信号上对第一信号进行编码，在时钟脉冲序列的节奏处通过m条引线的总线传输n个二进制信号，其中m

公开(公告)号：EP1439468A2

公开(公告)日：2004-07-21

申请号：EP03079150.3

申请日：2003-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F13/40

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: There is described a method that makes it possible to transmit n binary signals through a bus of m leads, where m

Abstract translation: 描述了一种使得可以通过在第二信号上对第一信号进行编码来通过m个引线的总线（其中m

公开(公告)号：EP1408405A1

公开(公告)日：2004-04-14

申请号：EP02425620.8

申请日：2002-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/30076 ,  G06F9/30181 ,  G06F9/3897

Abstract: A reconfigurable control structure for CPUs comprises a first control unit (UC0) with a first basic instruction set associated thereto, and a second control unit (UC1), with a second instruction set associated thereto. Associated to the second control unit (UC1) is at least one programming element (MCP, MCS) for rendering said second instruction set selectively modifiable. Also present is at least one circuit element (IR, 10) for supplying instruction codes to be executed to said first control unit (UC0) and to said second control unit (UC1), so that each instruction can be executed under the control of at least one between said first control unit (UC0) or said second control unit (UC1) according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

Abstract translation: 寄存器（IR，10）向第一和第二控制单元（UC0，UC1）提供要执行的指令代码，使得每个指令可以根据每个指令是否包含在至少一个控制单元的控制下执行 基本指令集和可选择性修改的指令集之间的至少一个。 还包括使用控制结构的过程的独立权利要求。

公开(公告)号：EP1383042B1

公开(公告)日：2007-03-28

申请号：EP02425469.0

申请日：2002-07-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F9/38

CPC classification number: G06F1/06 ,  G06F9/3869

公开(公告)号：EP1439468B1

公开(公告)日：2007-02-21

申请号：EP03079150.3

申请日：2003-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F13/40

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: There is described a method that makes it possible to transmit n binary signals through a bus of m leads, where m

公开(公告)号：EP1383042A1

公开(公告)日：2004-01-21

申请号：EP02425469.0

申请日：2002-07-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F9/38

CPC classification number: G06F1/06 ,  G06F9/3869

Abstract: A pipeline structure (200) for use in a digital system (110) is proposed. The pipeline structure includes a plurality of stages (ST i ) arranged in a sequence from a first stage (ST 1 ) for receiving an input of the pipeline structure to a last stage (ST 5 ) for providing an output of the pipeline structure, at least one intermediate stage (ST 2 -ST 4 ) being interposed between the first stage and the last stage, wherein the first stage and the last stage are controlled by a main clock signal (CLK m ); the pipeline structure further includes phase shifting means (D 2 -D 4 ) for generating at least one local clock signal (CLK 2 -CLK 4 ) from the main clock signal for controlling the at least one intermediate stage, the main clock signal and the at least one local clock signal being out of phase.

Abstract translation: 提出了一种用于数字系统（110）的管线结构（200）。 流水线结构包括以从第一级（ST1）的顺序排列的用于接收流水线结构的输入到最后级（ST5）的多级（STi），用于提供流水线结构的输出，至少一个中间 （ST2-ST4）插入在第一级和最后级之间，其中第一级和最后级由主时钟信号（CLKm）控制; 所述流水线结构还包括用于从所述主时钟信号产生至少一个本地时钟信号（CLK2-CLK4）的相移装置（D2-D4），用于控制所述至少一个中间级，所述主时钟信号和所述至少一个本地 时钟信号异相。