公开(公告)号：EP2299481A2

公开(公告)日：2011-03-23

申请号：EP10015719.7

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming in the first semiconductor layer (21) first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming in the first semiconductor layer (21) second sub-regions (D1, D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 用于制造集成在其上形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，其特征在于其包括以下步骤： - 在 在所述半导体衬底（100）上形成漏极外延层（20）的第一电阻率值（ρ1）的第一导电类型的第一半导体外延层（21）， - 在所述第一半导体层（21） 借助于具有第一注入剂量（Φ1P）的第一选择性注入步骤的第二导电类型的第一子区域（51）;在第一半导体层（21）中形成第二导电类型的第二子区域（D1，D1a） 借助于具有第二注入剂量（Φ1N）的第二注入步骤的第一导电类型， - 形成表面半导体层（23），其中形成第二导电类型的本体区域（40）与第一子区域 - 区域（51）， - carryin 形成热扩散工艺，使得第一子区域（51）形成与主体区域（40）对准并电接触的单个电连续柱状区域（50）。

公开(公告)号：EP1742259A1

公开(公告)日：2007-01-10

申请号：EP05425494.1

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming second sub-regions (D1,D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤： 至少形成在所述半导体衬底（100）上形成所述漏极外延层（20）的电阻率（α）的第一值的第一类型的导电性的第一半导体外延层（21）， - 形成所述第一子区域（51） 通过具有第一注入剂量（| 1P）的第一选择性注入步骤，通过第二种注入步骤形成第一类型导电性的第二子区域（D1，D1a） 第二植入剂量（| 1N）， - 形成表面半导体层（23），其中形成第二导电类型的体区（40）与第一子区（51）对准， - 执行热扩散过程 使得第一子区域（51）fo rm是单个电连续柱区域（50），其对准并与身体区域（40）电接触。

公开(公告)号：EP1742258A1

公开(公告)日：2007-01-10

申请号：EP05425493.3

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps:
forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (ρ 1 ) value on the semiconductor substrate (100),
forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (ρ 2 ) value on the first semiconductor layer (21),
forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (Φ 1 ) ,
forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (ρ 6 ) value,
forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1),
carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).

Abstract translation: 用于制造集成在第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，包括以下步骤：形成第一导电类型的第一半导体层（21）和第一导电类型的第一半导体层 在所述半导体衬底（100）上的第一电阻率（ρ1）值，在所述第一半导体层（21）上形成至少第二电阻率（ρ2）值的第二导电类型的第二半导体层（22），从而形成 通过具有第一注入剂量（Φ1）的第一选择注入步骤在该至少第二半导体层（22）上形成具有第一导电类型的第一多个注入区域（D1），在该至少一个注入区域 第二半导体层（22）;第三电阻率（ρ6）值的第一导电类型的表面半导体层（26），其在表面半导体层（26）中形成第二导电类型的体区域（40） 身体部位（ 40）与没有所述多个注入区域（D1）的所述半导体层（22）的部分对准，执行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续注入柱区域 D）沿所述至少第二半导体层（22）延伸，所述多个列注入区（D）限定与所述体区（40）对齐的所述第二导电类型的多个列区（50）。