公开(公告)号：EP1179839A2

公开(公告)日：2002-02-13

申请号：EP01114948.1

申请日：2001-06-20

Applicant: STMicroelectronics S.r.l.

Inventor： Bez, Roberto ,  Camerlenghi, Emilio ,  Ratti Stefano

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps:

forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2);
cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell;
filling the at least one trench (6) with an isolation layer (7);
depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and
etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

公开(公告)号：EP1179839A3

公开(公告)日：2004-12-15

申请号：EP01114948.1

申请日：2001-06-20

Applicant: STMicroelectronics S.r.l.

Inventor： Bez, Roberto ,  Camerlenghi, Emilio ,  Ratti Stefano

IPC: H01L21/336 ,  H01L21/8247 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

Abstract translation: 一种用于在半导体衬底上制造非易失性存储单元的工艺包括以下步骤：由氧化物层（2）形成由与衬底隔离的第一多晶硅层（3）组成的堆叠结构; 级联蚀刻第一多晶硅层（3），氧化物层（2）和半导体衬底（1）以限定电池的浮动栅极区域的第一部分和与有源区域（AA）接合的至少一个沟槽（6） 的记忆单元; 用隔离层（7）填充所述至少一个沟槽（6）; 在所述半导体的整个暴露表面上沉积第二多晶硅层（8）; 并蚀刻掉第二多晶硅层（8）以暴露形成在第一多晶硅层（3）中的浮栅区域，从而形成与第一多晶硅层（3）的上述部分相邻的延伸部（9）。