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    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions
    1.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions 审中-公开
    对于具有选择晶体管的双极单元阵列具有突出的导电区域的制造方法

    公开(公告)号：EP2015357A1

    公开(公告)日：2009-01-14

    申请号：EP07425423.6

    申请日：2007-07-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

    IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

    Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

    Process for manufacturing a memory device having selector transistors for storage elements and memory device fabricated thereby
    4.
    发明公开
    Process for manufacturing a memory device having selector transistors for storage elements and memory device fabricated thereby 有权
    一种用于制造具有用于存储元件的选择晶体管的蓄电装置，以及相应产生的存储装置的过程

    公开(公告)号：EP1475840A1

    公开(公告)日：2004-11-10

    申请号：EP03425292.4

    申请日：2003-05-07

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

    Abstract: A process for manufacturing a memory device having selector bipolar transistors (25) for storage elements (65), includes the steps of: in a semiconductor body (20), forming at least a selector transistor (25), having at least an embedded conductive region (26), and forming at least a storage element (65), stacked on and electrically connected to the selector transistor (25); moreover, the step of forming at least a selector transistor (25) includes forming at least a raised conductive region (35, 36) located on and electrically connected to the embedded conductive region (26).

    Abstract translation: 一种用于制造具有存储元件选择双极型晶体管（25）（65）的存储器器件的方法包括以下步骤：在半导体本体（20），形成至少上嵌入的导电至少具有选择晶体管（25） 区域（26），和至少形成存储元件（65），堆叠​​在并且电连接到选择晶体管（25）; 更完了，形成至少一个选择晶体管（25）的步骤包括形成至少位于并电连接到嵌入的导电区域（26）的凸起的导电区域（35，36）。

    Small area contact region, high efficiency phase change memory cell and fabrication method thereof
    5.
    发明公开
    Small area contact region, high efficiency phase change memory cell and fabrication method thereof 审中-公开
    小面积接触区域，高效率相变存储器元件及其制造方法

    公开(公告)号：EP1318552A1

    公开(公告)日：2003-06-11

    申请号：EP01128461.9

    申请日：2001-12-05

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Riva, Caterina ,  Zonca, Romina

    IPC: H01L45/00 ,  G11C11/34 ,  H01L27/24

    CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

    Abstract: A contact structure (30) in an electronic semiconductor device, including a first conducting region (31) having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region (32) having a second thin portion (32a) with a second sublithographic dimension in a second direction transverse to said first direction; the first and second conducting regions being in direct electrical contact at the first and second thin portions and defining a contact area (33) having a sublithografic extension, lower than 100 nm, preferably about 20 nm. The thin sublithographic portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer (34); the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic hard mask opening that is used to etch a mold opening (40) in a mold layer (38) and filling the mold opening.

    Abstract translation: 在半导体电子器件，其包括具有在第一方向上的第一亚光刻尺寸的第一薄壁部的第一导电区域（31）的接触结构（30）; 具有在第二方向上横向于所述第一方向的第二亚光刻尺寸的第二薄壁部（32A）的第二导电区（32）; 第一和第二导电区域在所述第一和第二薄膜部分直接电接触和限定具有sublithografic延伸的接触区域（33），低于100nm，优选约20nm。薄亚光刻的部分获得使用沉积代替 光刻的：所述第一薄壁部的设置于在第一电介质层（34）中的开口的壁; 所述第二薄壁部是通过在第一划界层的垂直壁罢免牺牲区域，在所述牺牲区域的自由侧罢免第二划界层，去除牺牲区域以形成亚光刻硬掩模开口获得并用于蚀刻 在模制层（38）和填充所述模具开口的模具开口（40）。

    Process of manufacture of a non volatile memory with electric continuity of the common source lines
    6.
    发明公开
    Process of manufacture of a non volatile memory with electric continuity of the common source lines 审中-公开
    来自莱顿根的Herstellungsverfahren von Festwertspeichern mit elektrischerKontinuitätgemeinsamer

    公开(公告)号：EP1045440A1

    公开(公告)日：2000-10-18

    申请号：EP99830211.1

    申请日：1999-04-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bez, Roberto ,  Riva, Caterina ,  Servalli, Giorgio

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521

    Abstract: Process for the manufacture of a non volatile memory with memory cells arranged in lines (2) and columns (3) in a matrix structure, with source lines (10) extending parallelly and intercalate to said lines (1), said source lines (10) formed by active regions intercalated to field oxide zones (4), said process comprising steps for the definition of active areas of said columns (3) of said matrix of non volatile memory cells and the definition of said field oxide zones (4), subsequent steps for the definition of the lines (2) of said matrix of non volatile memory cells, a following step for the definition of said source lines (10). In said step for the definition of the source lines a process step comprising a selective introduction of dopant is foreseen so to form a layer of buried silicon with high concentration of dopant (30), said layer of buried silicon (30) being formed to such a depth to coincide with the regions of silicon the underlying field oxide zones (4), a following introduction of dopant in said active regions of the source lines (10) to superficially contact said layer of buried silicon (30).

    Abstract translation: 用于制造具有以矩阵结构的线（2）和列（3）排列的存储单元的非易失性存储器的方法，源极线（10）平行并插入所述线（1），所述源极线（10） ）由所述有源区插入到场氧化物区（4）中形成，所述方法包括用于定义所述非易失性存储单元矩阵的所述列（3）的有效面积和所述场氧化物区（4）的定义的步骤， 用于定义非易失性存储器单元的所述矩阵的行（2）的后续步骤，用于定义所述源极线（10）的后续步骤。 在用于定义源极线的所述步骤中，预期包括选择性引入掺杂剂的工艺步骤，以便形成具有高浓度掺杂剂（30）的掩埋硅层，所述掩埋硅层（30）形成为 深度与硅的区域与下面的场氧化物区域（4）重合，随后在源极线（10）的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层（30）。

    A content addressable memory cell
    7.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP2261928A3

    公开(公告)日：2011-04-20

    申请号：EP10183801.9

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04 ,  G11C14/00

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    A content addressable memory cell
    8.
    发明公开
    A content addressable memory cell 有权
    内容可寻址存储单元

    公开(公告)号：EP2261928A2

    公开(公告)日：2010-12-15

    申请号：EP10183801.9

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Abstract translation: 一种用于非易失性内容可寻址存储器（100）的内容可寻址存储器单元（105），包括用于存储内容数字的非易失性存储装置（S1，S2，S），用于存储内容数字的选择输入（WLi; WLi，BLPj） 选择存储器单元，用于接收搜索数字（BLRj，BLLj）的搜索输入以及用于将搜索数字与内容数字进行比较并用于驱动存储器单元的匹配输出（MLi）以便发信号 内容数字和搜索数字之间的匹配。 非易失性存储装置包括至少一个用于以非易失性方式存储相应内容数字的相变存储器元件（S1，S2，S）。

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