公开(公告)号：EP1211516A1

公开(公告)日：2002-06-05

申请号：EP00830795.1

申请日：2000-11-30

Applicant: STMicroelectronics S.r.l.

Inventor： Signorelli, Tiziana ,  Pulvirenti, Francesco ,  Ribellino, Calogera

IPC: G01R31/30 ,  G06F11/00

CPC classification number: G06F11/006 ,  H01L2223/5444

Abstract: The invention relates to a circuit architecture and a relevant method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture of this invention comprises at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a means (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from the normal mode over to the trimming mode. This circuit architecture further comprises a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing up the non-volatile memory (3) state at power-on or at the simulating phase, and storing up the sequence (25) of trimming data at the programming phase; an interface (6) is provided between said pins (7,8,9) and the memory unit (2,3) for initially storing the data sequence (25) into the volatile memory unit and subsequently timing the trimming operation.

Abstract translation: 本发明涉及一种用于在应用板上直接执行修整操作，或者在封装集成电子设备的操作之后的相关方法。 本发明的电路架构包括至少一个具有非易失性存储元件（5）的非易失性存储器单元（3）和用于修改存储元件（5）的状态的装置（17,19），第一多功能 接收修剪数据的序列（25）的输入引脚（8），接收修整操作的定时信号的第二多功能输入引脚（9），以及用于切换电路架构操作的附加接入引脚（7） 从正常模式切换到修剪模式。 该电路架构还包括与非易失性存储器单元（3）相关联的易失性存储器单元（2），用于在上电或模拟阶段存储非易失性存储器（3）状态，并存储该序列 （25）在编程阶段修整数据; 在所述引脚（7,8,9）和存储器单元（2,3）之间提供接口（6），用于将数据序列（25）初始地存储到易失性存储器单元中，并且随后对修整操作进行定时。