公开(公告)号：EP1617324A1

公开(公告)日：2006-01-18

申请号：EP04016429.5

申请日：2004-07-13

Applicant: STMicroelectronics S.r.l.

Inventor： Lo Iacono, Daniele ,  Ronchi, Marco

IPC: G06F7/48 ,  H03M7/04

CPC classification number: G06F7/5332 ,  G06F7/4824 ,  G06F7/49994 ,  G06F7/508 ,  H03M7/04

Abstract: A system, such as e.g. a multiplier, for processing digital signals by using digital signals (x) in the Canonic Signed Digit (CSD) representation includes:

an input element (10) configured for making the digital signals (x) available in the Binary Canonic Signed Digit (BCSD) representation,
a converter (20) for converting the digital signals made available in the Binary Canonic Signed Digit (BCSD) representation into said Canonic Signed Digit (CSD) representation in view of use in processing.

The input element (10) may be a memory where the signals are stored in the Binary Canonic Signed Digit (BCSD) representation. Alternatively, the input element is adapted to be fed with digital signals (x) in the two's complement representation, and includes at least one converter (10) for converting the digital signals from the two's complement representation into the Binary Canonic Signed Digit (BCSD) representation. This preferably occurs via the T2I transformation, which leads to generating signals in the Canonic Signed Digit (CSD) representation, which are then converted to the Binary Canonic Signed Digit (BCSD) representation.

Abstract translation: 一种系统，例如 用于通过使用数字信号（x）来处理数字信号的乘法器，其特征在于包括：输入元件（10），被配置为使数字信号（x）可用于二进制加拿大签名数字（BCSD） 考虑到在处理中的使用，转换器（20）用于将二进制加拿大签名数字（BCSD）表示中可用的数字信号转换成所述加拿大签名数字（CSD）表示。 输入元件（10）可以是其中信号被存储在二进制加拿大签名数字（BCSD）表示中的存储器。 或者，输入元件适于以二进制补码表示的数字信号（x）馈送，并且包括至少一个转换器（10），用于将来自二进制补码表示的数字信号转换成二进制加拿大签名数字（BCSD） 表示。 这优选地通过T2I变换发生，这导致在加拿大签名数字（CSD）表示中产生信号，然后将其转换为二进制加拿大签名数字（BCSD）表示。

公开(公告)号：EP1617324B1

公开(公告)日：2007-09-12

申请号：EP04016429.5

申请日：2004-07-13

Applicant: STMicroelectronics S.r.l.

Inventor： Lo Iacono, Daniele ,  Ronchi, Marco

IPC: G06F7/48 ,  H03M7/04

CPC classification number: G06F7/5332 ,  G06F7/4824 ,  G06F7/49994 ,  G06F7/508 ,  H03M7/04

公开(公告)号：EP1328079A1

公开(公告)日：2003-07-16

申请号：EP02425011.0

申请日：2002-01-14

Applicant: STMicroelectronics S.r.l.

Inventor： Ronchi, Marco ,  Della Torre, Luigi

IPC: H04J11/00

CPC classification number: H04J13/0048 ,  H04J13/0044 ,  H04J13/18 ,  H04J13/20

Abstract: In communication systems such as CDMA systems, the information is transmitted by using encoded sequences ( c j ) consisting of orthogonal codes chosen from between Hadamard codes and OVSF codes. The symbols of the sequences are generated in a dynamic way as symbols b(r n r 1 r 0 , c n c 1 c 0 ) belonging to a respective matrix, according to the formula b ( r n .. r 1 r 0 , c n .. c 1 c 0 ) = c n ·r n ¯ ⊕ ¯ ... ⊕ ¯ c 2 · r 2 ¯ ⊕ ¯ r 1 · c 1 ¯ ⊕ ¯ c 0 · r 0 ¯    where r n r 1 r 0 , c n c 1 c 0 designate the row and column coordinates of the symbol expressed in binary form, and the symbol ⊕ designates the logic-sum operator,
   or according to the expressions equivalent to said formula in terms of Boolean algebra.

Abstract translation: 在通信系统中：例如CDMA系统中，信息是反式通过使用由从Hadamard码和OVSF码之间选择的正交码编码的序列（CJ）mitted。 序列的码元以动态的方式作为符号B（rnr1r0，cnc1c0）属于respectivement矩阵产生，gemäß式B（rn..r1r0，cn..c1c0）= cn.rn（+）.. （+）c2.r2（+）r1.c1（+）c0.r0其中rnr1r0，cnc1c0指定的行和列坐标以二进制形式表示所述符号，并且符号（+）表示该逻辑和运算器， 或gemäß到等于上述公式中布尔代数的术语表达。

公开(公告)号：EP1058451B1

公开(公告)日：2006-07-19

申请号：EP99830330.9

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Della Torre, Luigi ,  Ronchi, Marco ,  Vitali, Andrea

IPC: H04N5/455 ,  H03D1/22

CPC classification number: H03D1/00 ,  H04N5/455 ,  H04N21/4382

公开(公告)号：EP1058451A1

公开(公告)日：2000-12-06

申请号：EP99830330.9

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Della Torre, Luigi ,  Ronchi, Marco ,  Vitali, Andrea

IPC: H04N5/455

CPC classification number: H03D1/00 ,  H04N5/455 ,  H04N21/4382

Abstract: A digital AM demodulator, particularly for demodulating a signal (x) originating from a tuner, comprising:

means (13) for generating a first carrier (ω a t) which is not correlated with the input signal (x) to be demodulated;
first means (3) for multiplying the first carrier (ω a t) by the input signal (x) to be demodulated;
filtering means (1, 2), arranged upstream and downstream of said multiplier means (3) and adapted to eliminate unwanted spectral repeats;
the particularity of which is the fact that it comprises means (15) for detecting the phase shift between the pulse (ω i ) of the input signal (x) to be demodulated and a local carrier (ω o t) and means (18) for correlating the first carrier with the input signal, the first carrier and the local carrier being mutually correlated, the local carrier not being correlated with the input signal to be demodulated.

Abstract translation: 一种数字AM解调器，特别是用于解调来自调谐器的信号（x），包括：用于产生与要解调的输入信号（x）不相关的第一载波（ω）的装置（13） 第一装置（3），用于将第一载波（ωa）乘以待解调的输入信号（x）; 滤波装置（1,2），布置在所述乘法器装置（3）的上游和下游，并适于消除不需要的频谱重复; 其特征在于它包括用于检测要被解调的输入信号（x）的脉冲（ωi）与本地载波（ω）之间的相移的装置（15）和用于 将第一载波与输入信号相关，第一载波和本地载波相互相关，本地载波不与要解调的输入信号相关。

公开(公告)号：EP1058451B9

公开(公告)日：2006-10-25

申请号：EP99830330.9

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Della Torre, Luigi ,  Ronchi, Marco ,  Vitali, Andrea

IPC: H04N5/455 ,  H03D1/22

CPC classification number: H03D1/00 ,  H04N5/455 ,  H04N21/4382

公开(公告)号：EP1217724A1

公开(公告)日：2002-06-26

申请号：EP00830838.9

申请日：2000-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Ronchi, Marco ,  Della Torre, Luigi ,  Zambotti, Paolo ,  Vitali, Andrea

IPC: H03D3/00

CPC classification number: H03D3/007

Abstract: A digital demodulator for angle-modulated (PM, FM) signals comprises:

an input module (1, 2) for generating, starting from the modulated signal (s fm ), a first component (cosφ(n)) and a second component (sinφ(n)) in quadrature with respect to one another, said components in quadrature being representative of the real part and of the imaginary part of the modulating signal (s'(t); s"(t)) represented as a complex variable; and
a processing module (4) able to generate an output signal, calculating the arctangent function of the ratio between said imaginary part and said real part, the output signal identifying the demodulated signal (s'(t); s"(t)).

The processing module (4) acts on the components in quadrature either directly, in the case of phase demodulation, or indirectly, in the case of frequency demodulation. In the latter case, the above-mentioned real component and imaginary component are calculated, respectively, as the sum of the products of each of the components in quadrature with a corresponding delayed version, and as the difference of the cross products of each of the two components in quadrature with a version delayed in time of the other component in quadrature.
The demodulator may be implemented either as a dedicated hardware unit, or else resorting to a computer program product for DSP or microprocessor.

Abstract translation: 用于角度调制（PM，FM）信号的数字解调器包括：输入模块（1,2），用于从调制信号（sfm）开始产生第一分量（cosφ（n））和第二分量 sin（n））相互正交，所述正交分量表示调制信号的实部和虚部（s'（t）; s“（t）），表示为复数 变量;以及处理模块（4），其能够产生输出信号，计算所述虚部与所述实部之间的比值的反正切函数，所述输出信号识别解调信号（s'（t）; s“（t ））。 在频率解调的情况下，处理模块（4）在相位解调的情况下直接作用在正交的部件上。 在后一种情况下，分别计算上述实数分量和虚分量作为正交的每个分量的乘积与对应的延迟版本的和的总和，以及作为每个 正交的两个组件，其中正交的另一个组件的时间延迟版本。 解调器可以被实现为专用硬件单元，或者采用用于DSP或微处理器的计算机程序产品。

公开(公告)号：EP0967719A1

公开(公告)日：1999-12-29

申请号：EP98830386.3

申请日：1998-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： Angelici, Marco ,  Ronchi, Marco

IPC: H03H19/00

CPC classification number: H03H19/004

Abstract: The invention relates to a switched capacitor low-pass filter of a type which incorporates a plurality of integrator stages cascade connected together. The filter comprises at least one stage including the circuit device for cancelling out glitch pulses. This device is a deglitching circuit provided within the filter.
Preferably, each stage in the filter is formed of a deglitching device which acts as a smoothing integrator.

Abstract translation: 本发明涉及这样一种类型，集成了连接在一起的积分器级级联的多个开关电容器低通滤波器。 所述过滤器包括至少一个阶段包括用于消除毛刺脉冲电路装置。 该装置是过滤器内设置的deglitching电路。 优选地，在过滤器的每个阶段中形成一个deglitching设备充当平滑积分器。