公开(公告)号：EP1128594A1

公开(公告)日：2001-08-29

申请号：EP00830131.9

申请日：2000-02-24

Applicant: STMicroelectronics S.r.l.

Inventor： Guinea, Jesus ,  Rutar, Massimiliano ,  Tomasini, Luciano

IPC: H04L7/033 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07

CPC classification number: H03L7/07 ,  H03L7/0814 ,  H04L7/0083 ,  H04L7/0337

Abstract: A switching circuit for switching an output (CKS) to one of a plurality of N input clock signals (CK1-CKN) which are delayed relative to one another comprises circuit means (31-316, 7) responding to a control (CNT) in order to enable the transmission, on the output signal (CKS), of a new signal (CK(i-1); CKi) of the plurality of input signals which is advanced or delayed relative to a current signal (CKi; CK(i-1)) of the plurality of input signals which is currently transmitted on the output signal (CKS), the circuit means (31-316, 7) enabling the transmission of the new signal (CK(i-1); CKi) before disabling the transmission of the current signal (CKi; CK(i-1)) on the output signal (CKS) so as to prevent the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract translation: 用于将输出（CKS）切换为相对于彼此延迟的多个N个输入时钟信号（CK1-CKN）中的一个的切换电路包括响应于控制（CNT）的电路装置（31-316,77） 使得能够在输出信号（CKS）上传输相对于当前信号（CKi; CK（i（i））提前或延迟的多个输入信号的新信号（CK（i-1）; CKi） -1）），可以在输出信号（CKS）上发送的多个输入信号中，能够在新的信号（CK（i-1）; CKi）之前发送的电路装置（31-316,7） 禁止在输出信号（CKS）上传输当前信号（CKi; CK（i-1）），以防止在将输出信号从一个时钟信号切换到另一个时产生假信号。