Method for programming a memory device suitable to minimize floating gate complings and memory device
    1.
    发明公开
    Method for programming a memory device suitable to minimize floating gate complings and memory device 有权
    适于用于编程存储器装置中,浮置栅极伊甸联接器和一个存储器阵列的方法最小化

    公开(公告)号:EP1840901A1

    公开(公告)日:2007-10-03

    申请号:EP06425223.2

    申请日:2006-03-31

    CPC classification number: G11C11/5628 G11C16/10 G11C2211/5621

    Abstract: Method for programming a memory device (30) of the type comprising a matrix of memory cells (35) divided in buffers of cells (35) capacitively uncoupled from each other, the method comprising the steps of:
    - first programming of said cells (35) belonging to a buffer (B);
    - second programming of said cells (35) belonging to said buffer (B);
    said step of first programming occurs with a ramp gate voltage having first pitch (p1) and programs said cells of said buffer (B) with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch (p2) lower than the pitch (p1).
    The invention also relates to a memory device suitable for implementing the method proposed.

    Abstract translation: 用于编程的类型,其包括存储单元分成(35)细胞的缓冲器的矩阵(35)从海誓山盟电容去耦的存储器设备(30)的方法,该方法包括以下步骤: - 所述细胞的第一编程(35 )属于缓冲液(B); - 所述细胞属于所述缓冲液(B)第二编程(35); 第一编程的所述步骤与具有第一间距(P1)的斜坡的栅极电压发生和方案所述带具有斜坡栅极电压间距(P2)发生,并且所述缓冲器(B)具有更高的阈值分布的细胞第二编程的所述步骤低于 的间距(P1)。 因此本发明涉及一种适合于实施所提出的方法的存储装置。

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