公开(公告)号：EP1647991B1

公开(公告)日：2007-09-19

申请号：EP04105094.9

申请日：2004-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Mirichigni, Graziano ,  Martinelli, Andrea

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/0416 ,  G11C16/26

公开(公告)号：EP1498906B1

公开(公告)日：2008-12-31

申请号：EP03077228.9

申请日：2003-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Martinelli, Andrea ,  Balluchi, Daniele ,  Villa, Corrado

IPC: G11C29/00

CPC classification number: G11C29/83

公开(公告)号：EP1840901A1

公开(公告)日：2007-10-03

申请号：EP06425223.2

申请日：2006-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Martinelli, Andrea ,  Schippers Stefan ,  Onorato Marco

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

Abstract: Method for programming a memory device (30) of the type comprising a matrix of memory cells (35) divided in buffers of cells (35) capacitively uncoupled from each other, the method comprising the steps of:
- first programming of said cells (35) belonging to a buffer (B);
- second programming of said cells (35) belonging to said buffer (B);
said step of first programming occurs with a ramp gate voltage having first pitch (p1) and programs said cells of said buffer (B) with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch (p2) lower than the pitch (p1).
The invention also relates to a memory device suitable for implementing the method proposed.

Abstract translation: 用于编程的类型，其包括存储单元分成（35）细胞的缓冲器的矩阵（35）从海誓山盟电容去耦的存储器设备（30）的方法，该方法包括以下步骤： - 所述细胞的第一编程（35 ）属于缓冲液（B）; - 所述细胞属于所述缓冲液（B）第二编程（35）; 第一编程的所述步骤与具有第一间距（P1）的斜坡的栅极电压发生和方案所述带具有斜坡栅极电压间距（P2）发生，并且所述缓冲器（B）具有更高的阈值分布的细胞第二编程的所述步骤低于 的间距（P1）。 因此本发明涉及一种适合于实施所提出的方法的存储装置。

公开(公告)号：EP1647991A1

公开(公告)日：2006-04-19

申请号：EP04105094.9

申请日：2004-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Mirichigni, Graziano ,  Martinelli, Andrea

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/0416 ,  G11C16/26

Abstract: A semiconductor memory device (100) is disclosed. The semiconductor memory device includes a plurality of memory cells (110), arranged according to a plurality of rows and a plurality of column. The memory devices further includes a plurality of bit lines (BL1), each bit line being associated with a respective column of said plurality, and a selecting structure (130b) of the bit lines, to select at least one among said bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit (210, CL1, CL0, C 1 , C 2 ), adapted to causing the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

Abstract translation: 公开了一种半导体存储器件（100）。 半导体存储器件包括根据多行和多列布置的多个存储单元（110）。 存储器件还包括多个位线（BL1），每个位线与所述多个的相应列相关联，以及位线的选择结构（130b），以选择所述位线中的至少一个，保持 剩余的位线未选择。 所述存储器件还包括钳位电路（210，CL1，CL0，C 1，C 2），其适用于在对所述存储器的访问操作期间使与所选位线相邻的未选定位线的规定电压的钳位 。

公开(公告)号：EP1498906A1

公开(公告)日：2005-01-19

申请号：EP03077228.9

申请日：2003-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Martinelli, Andrea ,  Balluchi, Daniele ,  Villa, Corrado

IPC: G11C29/00

CPC classification number: G11C29/83

Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors (S1-Sn) and, associated with each memory sector, a respective memory location selector (1031-103n) for selecting memory locations within the memory sector according to an address (ADD). The redundancy scheme comprises at least one redundant memory sector (RS1-RSm) adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry (111) for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means (1131-113n) are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line (VXR). A memory sector unusable status indicator element (211) is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.

Abstract translation: 一种用于具有至少两个存储器扇区（S1-Sn）并且与每个存储器扇区相关联的存储器集成电路的冗余方案，用于根据地址来选择存储器扇区内的存储器位置的相应存储器位置选择器（1031-103n） 加）。 所述冗余方案包括适于功能地替代所述至少两个存储器扇区中的一个的至少一个冗余存储器扇区（RS1-RSm），以及冗余控制电路（111），用于使被声明为不可用的存储器扇区的功能替换 所述至少一个冗余存储器扇区中的一个; 冗余控制电路检测对不可用存储器扇区内的存储器位置的访问请求，并将访问请求转发到冗余存储器扇区中的相应冗余存储器位置。 与每个存储器位置选择器相关联，提供相应的电源控制装置（1131-113n），其适于选择性地将相关联的存储器位置选择器连接/断开与电源分配线（VXR）的连接/断开。 存储器扇区不可用状态指示器元件（211）与每个存储器扇区相关联，用于控制相应的电源控制装置，以便在设置时引起各个存储器位置选择器与电源分配线的选择性断开。