Voltage regulation system for a multibit programming of a reduced integration area non volatile memory
    1.
    发明公开
    Voltage regulation system for a multibit programming of a reduced integration area non volatile memory 有权
    系统用于具有减小的面积的集成的紧凑的非易失性存储器的多比特的编程电压控制

    公开(公告)号:EP1453057A1

    公开(公告)日:2004-09-01

    申请号:EP03425133.0

    申请日:2003-02-28

    CPC classification number: G11C11/5628

    Abstract: The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix (5) organised in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Memory cells have drain terminals (D) connected to matrix columns and biased in the programming step with a predetermined voltage value by means of program load circuits (2) associated to each matrix column; advantageously, the invention provides, in parallel with each program load circuit (2), a conduction-to-ground path (9) enabled by a controlled active element (10).

    Abstract translation: 本发明涉及一种用于在非易失性存储器的多字编程,对于闪存类型的实施例,具有低的电路面积占用一个电压调节系统,worin存储器包括至少一个存储单元矩阵(5)在细胞的行和列,并与对应有组织 电路负责处理,解码,读,写和擦除的存储单元的内容。 存储器单元具有由程序负载电路被连接到矩阵的列和在编程步骤的预定电压值偏置漏极端子(D)(2)关联到每个矩阵列; 有利地,本发明提供,在与各个节目负载电路(2),(9)由一个控制的有源元件(10)使能导通到地路径平行。

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