公开(公告)号：EP0928068A1

公开(公告)日：1999-07-07

申请号：EP97830743.7

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mulatti, Jacopo ,  Maccarrone, Marco ,  Martines, Ignazio ,  Micheloni, Rino

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016

Abstract: The invention relates to a low-consumption TTL-CMOS input buffer stage (10) of the type which comprises a chain of inverters (11,12,13,14) cascade connected between an input (APAD) receiving electric signals at a TTL logic level and an output (ADD) reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference (Vcc) and a second or ground reference (GND). Advantageously, the first inverter (11) in the chain includes a means (15,MP2,MN2) of selecting the delivery path to the stage (10) according to an activate signal (LOWPOWER) for a low-consumption operation mode.
In essence, the first inverter (11) of the buffer (10) has two signal paths, one for normal operation, and the other for low consumption operation.

Abstract translation: 本发明涉及一种低功耗TTL-CMOS输入缓冲器级（10），其包括串联连接在以TTL逻辑电路接收电信号的输入端（APAD）之间的反相器链（11,12,13,14） 电平和输出（ADD）以CMOS逻辑电平再现电信号，并且在第一或电源电压参考（Vcc）和第二或接地参考（GND）之间供电。 有利地，链中的第一反相器（11）包括根据用于低功耗操作模式的激活信号（LOWPOWER）选择到级（10）的传送路径的装置（15，MP2，MN2）。 实质上，缓冲器（10）的第一反相器（11）具有两个信号路径，一个用于正常操作，另一个用于低功耗操作。

公开(公告)号：EP1640995A1

公开(公告)日：2006-03-29

申请号：EP04425724.4

申请日：2004-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Martines, Ignazio ,  La Placa, Michele

IPC: G11C16/28

CPC classification number: G11C16/28

Abstract: Described herein is a reading circuit (5) for a nonvolatile memory device (1), wherein the currents flowing through an array memory cell (12) to be read, and a reference memory cell (15) with known contents, are converted into an array voltage (V M ) and, respectively, into a reference voltage (V R ), which are compared to determine the contents of the array memory cell (12). The method envisages reducing the electrical stress to which the reference memory cell (15) is subjected during reading, by generating and holding a sample (V 2 ) of the reference voltage (V R ), then deselecting the reference memory cell (15), and then continuing reading using the sample (V 2 ) of the reference voltage (V R ).

Abstract translation: 这里描述了一种用于非易失性存储器件（1）的读取电路（5），其中流过待读取的阵列存储单元（12）的电流和具有已知内容的参考存储单元（15）被转换为 阵列电压（VM）和分别变成参考电压（VR），其被比较以确定阵列存储单元（12）的内容。 该方法设想通过产生和保持参考电压（VR）的样本（V 2），然后取消选择参考存储单元（15），减少参考存储单元（15）在读取期间经受的电应力，以及 然后使用参考电压（VR）的采样（V 2）继续读取。

公开(公告)号：EP1453059B1

公开(公告)日：2005-10-12

申请号：EP03425134.8

申请日：2003-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Martines, Ignazio ,  Torrisi, Davide

IPC: G11C16/12

CPC classification number: G11C16/10 ,  G11C16/3404

公开(公告)号：EP1306975A1

公开(公告)日：2003-05-02

申请号：EP01830675.3

申请日：2001-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Curatolo, Giacomo ,  Martines, Ignazio ,  Torrisi, Davide

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K19/00361 ,  H03K17/167

Abstract: An output buffer for causing a voltage ( Vout ) of an integrated circuit output line ( OUT,OUT_PAD ) to switch from a voltage of a first voltage line ( VDD ) to a voltage of a second voltage line ( GND ) and vice versa, comprises a current path switch circuit ( 111a, 111b ) activatable for causing a prescribed current ( Is ) to constantly flow between the first and second voltage lines during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated ( Ic1 ) to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by that voltage line, among the first and second voltage lines, which plays an active role is thus kept substantially constant in the output line switching. In this way, the time derivative of the current flowing between the first and the second voltage lines is kept small and low switching noise is induced.

Abstract translation: 一种用于使集成电路输出线（OUT，OUT_PAD）的电压（Vout）从第一电压线（VDD）的电压切换到第二电压线（GND）的电压的输出缓冲器，反之亦然，包括 一个电流路径切换电路（111a，111b），用于在输出线两次连续切换之间的时间内使规定电流（Is）恒定地在第一和第二电压线之间流动，并使规定电流偏离 （Ic1）在从第一电压线电压切换到第二电压线电压的输出线的至少初始相位期间到输出线，反之亦然。 因此，在输出线切换中，起着主动作用的第一和第二电压线之间由该电压线传递的电流基本保持恒定。 以这种方式，在第一和第二电压线之间流动的电流的时间导数保持较小，并且引起低的开关噪声。

公开(公告)号：EP1742361A1

公开(公告)日：2007-01-10

申请号：EP05106180.2

申请日：2005-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： La Placa, Michele ,  Martines, Ignazio

IPC: H03K17/16

CPC classification number: H03K19/00384 ,  H03K17/167

Abstract: A self-adaptive output buffer ( 130 ) for an output terminal of an electronic circuit ( 100 ) suitable to be connected to a load ( Cload ) is proposed. The self-adaptive output buffer includes means for sensing ( 205 ) an indication of the capacitance of the load and means for driving ( 210 ) the load according to the sensing, wherein the means for sensing ( 205 ) includes capacitive means ( C S1 ) with a preset capacitance, means ( P S1 , N S1 ) for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring ( 230 , 225 ) a measuring voltage at the capacitive means due to a charge sharing between the capacitive means ( C S1 ) and the load ( Cload ).

Abstract translation: 提出了一种用于适于连接到负载（Cload）的电子电路（100）的输出端子的自适应输出缓冲器（130）。 自适应输出缓冲器包括用于感测（205）负载的电容的指示的装置和用于根据感测来驱动（210）负载的装置，其中感测装置（205）包括电容装置（C S1） 具有预置电容，用于将电容装置充电到预设电压的装置（P S1，N S1），用于将充电的电容装置与负载耦合的装置，以及用于在电容装置处测量（230,225）测量电压的装置 由于电容装置（C S1）和负载（Cload）之间的电荷共享。

公开(公告)号：EP1736844A1

公开(公告)日：2006-12-27

申请号：EP05425440.4

申请日：2005-06-20

Applicant: STMicroelectronics S.r.l.

Inventor： Martines, Ignazio ,  La Placa, Michele

IPC: G05F3/24

CPC classification number: G05F3/242

Abstract: Herein described is a basic electronic circuit suitable for generating a magnitude (Iref; T). The circuit has certain structural characteristics and the magnitude undergoes variations in function of the structural characteristics of the circuit. The circuit comprises at least two circuit parts (1, 2; 100, 200) suitable for supplying respective fractions (I1, I2; T1, T2) of the magnitude (Iref; T) and the at least two circuit parts (1, 2; 100, 200) have different structural characteristics.

Abstract translation: 这里描述了适用于产生幅度（Iref; T）的基本电子电路。 该电路具有一定的结构特征，并且幅度经历电路结构特性功能的变化。 该电路包括适于提供幅度（Iref; T）和至少两个电路部分（1,2）的各个分数（I1，I2; T1，T2）的至少两个电路部分（1,2; 100,200） ; 100,200）具有不同的结构特征。

公开(公告)号：EP1453059A1

公开(公告)日：2004-09-01

申请号：EP03425134.8

申请日：2003-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Martines, Ignazio ,  Torrisi, Davide

IPC: G11C16/12

CPC classification number: G11C16/10 ,  G11C16/3404

Abstract: The present invention relates to a gate voltage regulation system for the programming and/or soft programming phase of non volatile memory cells, for example of the Flash type, with low circuit area occupation, wherein memory cells (5) are organised in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content; the cells having gate terminals (G) biased in the programming phase with a predetermined voltage value by means of charge pump voltage regulators. Advantageously, a first (ST1) and a second (ST2) regulation stages are provided, being structurally independent, responsible for the programming and soft programming phase respectively; the first stage (ST1) generating a supply voltage for said second stage (ST2).

Abstract translation: 本发明涉及一种用于非易失性存储器单元的编程和/或软编程阶段的栅极电压调节系统，例如具有低电路面积占用的闪存类型，其中存储单元（5）被组织在具有 相应的电路负责寻址，解码，读取，写入和擦除存储器单元内容; 具有栅极端子（G）的电池通过电荷泵电压调节器以预定电压值偏置在编程阶段。 有利地，在结构上独立地提供分别负责编程和软编程阶段的第一（ST1）和第二（ST2）调节级; 产生用于所述第二级的电源电压的第一级（ST1）（ST2）。

公开(公告)号：EP1453057A1

公开(公告)日：2004-09-01

申请号：EP03425133.0

申请日：2003-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Martines, Ignazio ,  Scordaci, Massimo

IPC: G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix (5) organised in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Memory cells have drain terminals (D) connected to matrix columns and biased in the programming step with a predetermined voltage value by means of program load circuits (2) associated to each matrix column; advantageously, the invention provides, in parallel with each program load circuit (2), a conduction-to-ground path (9) enabled by a controlled active element (10).

Abstract translation: 本发明涉及一种用于在非易失性存储器的多字编程，对于闪存类型的实施例，具有低的电路面积占用一个电压调节系统，worin存储器包括至少一个存储单元矩阵（5）在细胞的行和列，并与对应有组织 电路负责处理，解码，读，写和擦除的存储单元的内容。 存储器单元具有由程序负载电路被连接到矩阵的列和在编程步骤的预定电压值偏置漏极端子（D）（2）关联到每个矩阵列; 有利地，本发明提供，在与各个节目负载电路（2），（9）由一个控制的有源元件（10）使能导通到地路径平行。

公开(公告)号：EP1742361B1

公开(公告)日：2009-09-09

申请号：EP05106180.2

申请日：2005-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： La Placa, Michele ,  Martines, Ignazio

IPC: H03K17/16

CPC classification number: H03K19/00384 ,  H03K17/167

公开(公告)号：EP1640995B1

公开(公告)日：2009-06-17

申请号：EP04425724.4

申请日：2004-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Martines, Ignazio ,  La Placa, Michele

IPC: G11C16/28

CPC classification number: G11C16/28