公开(公告)号：EP1870687A1

公开(公告)日：2007-12-26

申请号：EP06425430.3

申请日：2006-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Ziglioli, Federico ,  Combi, Chantal ,  Baldo, Lorenzo ,  Riva, Caterina ,  Shaw, Mark Andrew

IPC: G01L19/00 ,  G01L9/00

CPC classification number: G01L19/0038

Abstract: Described herein is an assembly (30) of an integrated device (1) and of a cap (32) coupled to the integrated device; the integrated device (1) is provided with at least a first and a second region (16, 17) to be fluidically accessed from outside, and the cap (32) has an outer portion (32a) provided with at least a first and a second inlet port (35, 36) in fluid communication with the first and second regions (16, 17). In particular, the first and second regions (16, 17) are arranged on a first outer face (20a), or on respective adjacent outer faces (20a, 20c), of the integrated device (1), and an interface structure (38) is set between the integrated device (1) and the outer portion (32a) of the cap (32), and is provided with a channel arrangement (39, 40) for routing the first and second regions (16, 17) towards the first and second inlets (35, 36).

Abstract translation: 在所描述的是一个集成的装置的组件（30）（1）耦合到所述集成装置的帽（32）的和; 集成器件（1）设置有至少一个第一和一个第二区域（16，17）以流体方式从外部访问，并且所述盖（32）具有在设置有至少一个第一和一个外部分（32A） 在与所述第一和第二区域（16,17）流体连通的第二入口端口（35，36）。 特别地，所述第一和第二区域（16,17）被布置在第一外表面（20A）上或集成器件（1），以及respectivement相邻的外表面（20A，20C）（对接结构38 ）被设置在集成器件（1）和盖（32的外部分（32A）之间），设置有用于朝向所述路由所述第一和第二区域（16,17）的信道配置（39,40） 第一和第二入口（35，36）。

公开(公告)号：EP2272794A1

公开(公告)日：2011-01-12

申请号：EP10184071.8

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package comprising a substrate (20) and a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b) and a damage-sensitive device mounted on top of the upper solder mask layer. Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21 a) that is to be covered by the damage-sensitive device (21), a plurality of vias (19) being positioned so that the vias substantially coincide with an outline of said damage-sensitive device (21) that the semiconductor package substrate (20) is intended to support.
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种包括基板（20）和损伤敏感装置（21）的半导体封装，包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）和安装在所述上焊接掩模层的顶部上的损伤敏感器件 。 有利地，多个通孔（19）根据待被损伤敏感设备（21）覆盖的区域（21a）中的均匀图案基本上分布，多个通孔（19）被定位成使得 通孔基本上与半导体封装衬底（20）旨在支撑的所述损伤敏感器件（21）的轮廓一致。 还描述了制造这种半导体封装基板的方法。

公开(公告)号：EP1878692A1

公开(公告)日：2008-01-16

申请号：EP06014651.1

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package substrate (20) suitable for supporting a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b). Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21a) that is to be covered by the damage-sensitive device (21).
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种适于支撑损伤敏感器件（21）的半导体封装衬底（20），包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）。 有利的是，多个通孔（19）在要被损伤敏感装置（21）覆盖的区域（21a）中根据均匀的图案基本分布。 还描述了制造这种半导体封装基板的方法。