公开(公告)号：EP1870687A1

公开(公告)日：2007-12-26

申请号：EP06425430.3

申请日：2006-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Ziglioli, Federico ,  Combi, Chantal ,  Baldo, Lorenzo ,  Riva, Caterina ,  Shaw, Mark Andrew

IPC: G01L19/00 ,  G01L9/00

CPC classification number: G01L19/0038

Abstract: Described herein is an assembly (30) of an integrated device (1) and of a cap (32) coupled to the integrated device; the integrated device (1) is provided with at least a first and a second region (16, 17) to be fluidically accessed from outside, and the cap (32) has an outer portion (32a) provided with at least a first and a second inlet port (35, 36) in fluid communication with the first and second regions (16, 17). In particular, the first and second regions (16, 17) are arranged on a first outer face (20a), or on respective adjacent outer faces (20a, 20c), of the integrated device (1), and an interface structure (38) is set between the integrated device (1) and the outer portion (32a) of the cap (32), and is provided with a channel arrangement (39, 40) for routing the first and second regions (16, 17) towards the first and second inlets (35, 36).

Abstract translation: 在所描述的是一个集成的装置的组件（30）（1）耦合到所述集成装置的帽（32）的和; 集成器件（1）设置有至少一个第一和一个第二区域（16，17）以流体方式从外部访问，并且所述盖（32）具有在设置有至少一个第一和一个外部分（32A） 在与所述第一和第二区域（16,17）流体连通的第二入口端口（35，36）。 特别地，所述第一和第二区域（16,17）被布置在第一外表面（20A）上或集成器件（1），以及respectivement相邻的外表面（20A，20C）（对接结构38 ）被设置在集成器件（1）和盖（32的外部分（32A）之间），设置有用于朝向所述路由所述第一和第二区域（16,17）的信道配置（39,40） 第一和第二入口（35，36）。

公开(公告)号：EP2202791A3

公开(公告)日：2011-04-13

申请号：EP10160512.9

申请日：2005-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

IPC: H01L23/48 ,  H01L21/762

CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a body (1) and, in the body (1): a semiconductor substrate (2), a semiconductor structural layer (10) and a dielectric layer (12) therebetween. A through interconnection via (30) traverses the body (1) and extends through the dielectric layer (12). The through interconnection via (30) has: a front-side interconnection region (17), including a portion of the structural layer (10) that extends between the dielectric layer (12) and a front face (10a) of the body (1) and is laterally insulated from the remainder of the structural layer (10); a back-side interconnection region (27), including a portion of the substrate (2) that extends between the dielectric layer (12) and a back face (2a) of the body (1) and is laterally insulated from the remainder of the substrate (2) by a back-side insulation trench (29). The back-side insulation trench (29) extends across the entire substrate (2; 102; 202), from the back face (2a) of the body (1) to the dielectric layer (12) the; and a conductive continuity region (8) connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

公开(公告)号：EP2194391B1

公开(公告)日：2012-04-04

申请号：EP09177168.3

申请日：2009-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Caterina ,  Morelli, Marco ,  Marchesi, Marco

IPC: G01R33/05 ,  G01R33/07

CPC classification number: G01R33/05 ,  G01R33/07

公开(公告)号：EP2202791A2

公开(公告)日：2010-06-30

申请号：EP10160512.9

申请日：2005-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

IPC: H01L23/48 ,  H01L21/762

CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a body (1) and, in the body (1): a semiconductor substrate (2), a semiconductor structural layer (10) and a dielectric layer (12) therebetween. A through interconnection via (30) traverses the body (1) and extends through the dielectric layer (12). The through interconnection via (30) has: a front-side interconnection region (17), including a portion of the structural layer (10) that extends between the dielectric layer (12) and a front face (10a) of the body (1) and is laterally insulated from the remainder of the structural layer (10); a back-side interconnection region (27), including a portion of the substrate (2) that extends between the dielectric layer (12) and a back face (2a) of the body (1) and is laterally insulated from the remainder of the substrate (2) by a back-side insulation trench (29). The back-side insulation trench (29) extends across the entire substrate (2; 102; 202), from the back face (2a) of the body (1) to the dielectric layer (12) the; and a conductive continuity region (8) connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

Abstract translation: 一种半导体器件包括主体（1），并且在主体（1）中：半导体衬底（2），半导体结构层（10）和其间的介电层（12）。 （30）的直通互连穿过主体（1）并延伸穿过介电层（12）。 （30）的贯穿互连具有：正面互连区域（17），其包括在介电层（12）和主体（1）的正面（10a）之间延伸的结构层（10）的一部分 ）并且与结构层（10）的其余部分横向绝缘; 包括在所述介电层（12）和所述主体（1）的背面（2a）之间延伸的所述衬底（2）的一部分的背侧互连区域（27），并且与所述衬底 衬底（2）通过背侧绝缘沟槽（29）。 背面绝缘沟槽（29）从主体（1）的背面（2a）延伸到整个衬底（2; 102; 202）到介电层（12） 以及通过介电层（12）连接前侧互连区域（17）和后侧互连区域（27）的导电连续区域（8）。

公开(公告)号：EP1788624A1

公开(公告)日：2007-05-23

申请号：EP05425807.4

申请日：2005-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

IPC: H01L23/48

CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body (1) comprising a structural layer (10), a substrate (2), and a dielectric layer (12) set between the structural layer (10) and the substrate (2); insulating a portion of the structural layer (10) to form a front-side interconnection region (17); insulating a portion of the substrate (2) to form a back-side interconnection region (27); and connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

Abstract translation: 在半导体器件中制造通孔的方法包括以下步骤：形成包括结构层（10），基底（2）和设置在结构层（10）之间的介电层（12）的主体（1） ）和基板（2）; 绝缘所述结构层（10）的一部分以形成正面互连区域（17）; 绝缘所述基板（2）的一部分以形成背面互连区域（27）; 并且通过电介质层（12）将前侧互连区域（17）和背面侧互连区域（27）连接起来。

公开(公告)号：EP1318552A1

公开(公告)日：2003-06-11

申请号：EP01128461.9

申请日：2001-12-05

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Riva, Caterina ,  Zonca, Romina

IPC: H01L45/00 ,  G11C11/34 ,  H01L27/24

CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

Abstract: A contact structure (30) in an electronic semiconductor device, including a first conducting region (31) having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region (32) having a second thin portion (32a) with a second sublithographic dimension in a second direction transverse to said first direction; the first and second conducting regions being in direct electrical contact at the first and second thin portions and defining a contact area (33) having a sublithografic extension, lower than 100 nm, preferably about 20 nm. The thin sublithographic portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer (34); the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic hard mask opening that is used to etch a mold opening (40) in a mold layer (38) and filling the mold opening.

Abstract translation: 在半导体电子器件，其包括具有在第一方向上的第一亚光刻尺寸的第一薄壁部的第一导电区域（31）的接触结构（30）; 具有在第二方向上横向于所述第一方向的第二亚光刻尺寸的第二薄壁部（32A）的第二导电区（32）; 第一和第二导电区域在所述第一和第二薄膜部分直接电接触和限定具有sublithografic延伸的接触区域（33），低于100nm，优选约20nm。薄亚光刻的部分获得使用沉积代替 光刻的：所述第一薄壁部的设置于在第一电介质层（34）中的开口的壁; 所述第二薄壁部是通过在第一划界层的垂直壁罢免牺牲区域，在所述牺牲区域的自由侧罢免第二划界层，去除牺牲区域以形成亚光刻硬掩模开口获得并用于蚀刻 在模制层（38）和填充所述模具开口的模具开口（40）。

公开(公告)号：EP1045440A1

公开(公告)日：2000-10-18

申请号：EP99830211.1

申请日：1999-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Bez, Roberto ,  Riva, Caterina ,  Servalli, Giorgio

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521

Abstract: Process for the manufacture of a non volatile memory with memory cells arranged in lines (2) and columns (3) in a matrix structure, with source lines (10) extending parallelly and intercalate to said lines (1), said source lines (10) formed by active regions intercalated to field oxide zones (4), said process comprising steps for the definition of active areas of said columns (3) of said matrix of non volatile memory cells and the definition of said field oxide zones (4), subsequent steps for the definition of the lines (2) of said matrix of non volatile memory cells, a following step for the definition of said source lines (10). In said step for the definition of the source lines a process step comprising a selective introduction of dopant is foreseen so to form a layer of buried silicon with high concentration of dopant (30), said layer of buried silicon (30) being formed to such a depth to coincide with the regions of silicon the underlying field oxide zones (4), a following introduction of dopant in said active regions of the source lines (10) to superficially contact said layer of buried silicon (30).

Abstract translation: 用于制造具有以矩阵结构的线（2）和列（3）排列的存储单元的非易失性存储器的方法，源极线（10）平行并插入所述线（1），所述源极线（10） ）由所述有源区插入到场氧化物区（4）中形成，所述方法包括用于定义所述非易失性存储单元矩阵的所述列（3）的有效面积和所述场氧化物区（4）的定义的步骤， 用于定义非易失性存储器单元的所述矩阵的行（2）的后续步骤，用于定义所述源极线（10）的后续步骤。 在用于定义源极线的所述步骤中，预期包括选择性引入掺杂剂的工艺步骤，以便形成具有高浓度掺杂剂（30）的掩埋硅层，所述掩埋硅层（30）形成为 深度与硅的区域与下面的场氧化物区域（4）重合，随后在源极线（10）的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层（30）。