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    CAD for redundant memory devices
    1.
    发明公开
    CAD for redundant memory devices 失效
    CADfürredundanten Speichervorrichtungen

    公开(公告)号：EP0911747A1

    公开(公告)日：1999-04-28

    申请号：EP97830525.8

    申请日：1997-10-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Capocelli, Piero ,  Taliercio, Michele ,  Varambally, Rajamohan ,  Baroni, Andrea

    IPC: G06F17/50 ,  G06F11/20

    CPC classification number: G11C29/72

    Abstract: A memory device generator for generating memory devices in a CAD environment, the generator comprising: a library means (4) containing predefined basic circuit components; memory array generation means (2) interacting with the library means (4) for generating a variable-size memory array (3) comprising a variable number of memory elements (R,C), and at least one redundant memory element (RR0-RR6); memory element selection circuit generation means (6,9,30) interacting with the library means (4) for generating a memory element selection circuit (7,10;7,10-1 to 10-n) to be associated with the memory array for selecting at least one memory element according to memory device address inputs (RADD,CADD). The memory element selection circuit generation means (6,9,30) comprises means for generating a variable-size content-addressable memory means (7,10;7,10-1 to 10n) having a plurality of content-addressable memory locations (8,12) each one associated to at least one respective memory element (R,C) or to the at least one redundant memory element (RR0-RR6), each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value.

    Abstract translation: 一种用于在CAD环境中生成存储器件的存储器件发生器，所述发生器包括：库装置（4），其包含预定义的基本电路部件; 存储器阵列生成装置（2）与用于生成包括可变数量的存储器元件（R，C）的可变大小的存储器阵列（3）的库装置（4）以及至少一个冗余存储元件（RR0-RR6 ）; 存储器元件选择电路产生装置（6,9,30）与库装置（4）相互作用，用于产生与存储器阵列相关联的存储元件选择电路（7,10; 7,10-1至10-n） 用于根据存储器设备地址输入（RADD，CADD）选择至少一个存储器元件。 存储元件选择电路产生装置（6,9,30）包括用于产生具有多个可内容寻址存储器位置的可变大小内容寻址存储装置（7,10; 7,10-1至10n）的装置 8,12），每个与至少一个相应的存储元件（R，C）或至少一个冗余存储器元件（RR0-RR6）相关联，每个内容可寻址存储器位置适于存储一组 当存储器件地址输入取一个值时，存储器件地址输入的值和用于选择相应存储元件或冗余存储器元件的值。

    Memory device with reduced power dissipation
    3.
    发明公开
    Memory device with reduced power dissipation 失效
    Speicherannnung mit vermindertem Leistungsverlust

    公开(公告)号：EP0869506A1

    公开(公告)日：1998-10-07

    申请号：EP97830160.4

    申请日：1997-04-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baroni, Andrea ,  Rimondi, Danilo ,  Taliercio, Michele ,  Torelli, Cosimo

    IPC: G11C7/00 ,  G11C11/409

    CPC classification number: G11C7/14 ,  G11C11/419

    Abstract: A memory device comprises an array (1) of memory cells (2,DMC0-DMCn) arranged in rows (R1-Rn) and columns (C1-Cm,DC), a plurality of gates (RD1-RDn) for transmitting respective selection outputs (RS1-RSn) of a row decoder (3) to respective rows (RS), a dummy column (DC) of dummy memory cells (DMC0-DMCn) substantially indentical to the memory cells, precharge means (P4,P5,P6,P7) for precharging the columns and the dummy column at a precharge potential (VDD) when no row is selected, and programming means (N7,N8,7) for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means (P3) for presetting the dummy memory cells in a first logic state when no row is selected; dummy column programming means (N9,N10) for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state; first detector means (DET1) for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of said gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from said first logic state to said second logic state.

    Abstract translation: 存储器件包括排列成行（R1-Rn）和列（C1-Cm，DC）的存储器单元阵列（2，DMC-DMCn），用于传输各个选择的多个栅极（RD1-RDn） 行解码器（3）的输出（RS1-RSn）到各行（RS），与存储单元基本上不相邻的虚拟存储单元（DMC0-DMCn）的虚拟列（DC），预充电装置（P4，P5，P6 ，P7），用于在未选择行时将列和虚拟列预充电为预充电电位（VDD），以及用于在各个编程电位设置所选列的编程装置（N7，N8,7）。 该装置包括用于在没有行被选择时以第一逻辑状态预设虚拟存储器单元的伪存储单元预设装置（P3） 用于将虚拟列设置在与第一逻辑状态相反的第二逻辑状态对应的规定编程电位的虚拟列编程装置（N9，N10） 第一检测器装置（DET1），用于检测虚拟列已经从预充电电位放电到规定编程电位，并因此启用所述多个门。 每个所述门具有耦合到相应的虚拟存储器单元的输入，使得一旦所述虚拟存储器单元从所述第一逻辑状态切换到所述第二逻辑状态，所述门被禁用。

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