公开(公告)号：EP0869506B1

公开(公告)日：2003-07-02

申请号：EP97830160.4

申请日：1997-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： Baroni, Andrea ,  Rimondi, Danilo ,  Taliercio, Michele ,  Torelli, Cosimo

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C7/14 ,  G11C11/419

公开(公告)号：EP1324340A1

公开(公告)日：2003-07-02

申请号：EP01830819.7

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rimondi, Danilo ,  Torelli, Cosimo

IPC: G11C7/20 ,  G11C11/419

CPC classification number: G11C7/20 ,  G11C11/419

Abstract: A memory cell comprises a first and a second inverters ( 103a,103b ) connected in a latch configuration. The inverters have respective first and second means ( SP1,SN1,SP2,SN2 ) for receiving a first and a second voltage supplies ( VDD,GND ), respectively. The cell also comprises means ( STa,STb ), responsive to a memory cell selection signal ( SEL ), for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line ( I/O,I/ON ), carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For flash-clearing the memory cell, means ( SWa,SWb ) are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device.

Abstract translation: 存储单元包括以锁存配置连接的第一和第二反相器（103a，103b）。 逆变器具有用于分别接收第一和第二电压源（VDD，GND）的相应的第一和第二装置（SP1，SN1，SP2，SN2）。 单元还包括响应于存储单元选择信号（SEL）的装置（STa，STb），用于选择性地将第一和第二反相器中的至少一个的输入连接到至少一个相应的输入/输出数据线（I / O，I / ON），在存储单元写入操作中携带要写入存储单元的输入数据，以及在存储器单元读取操作中从存储单元读取的输出数据。 为了闪存存储单元，提供装置（SWa，SWb），用于在第一电压源和第二电压源之间切换第一和第二反相器中的至少一个的第一和第二电压供应接收装置中的至少一个 。 存储器单元特别适于在存储器件中实现闪光功能。

公开(公告)号：EP1191601A1

公开(公告)日：2002-03-27

申请号：EP00830628.4

申请日：2000-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola ,  Atti, Massimo ,  Palumbo, Elisabetta ,  Torelli, Cosimo

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L29/7835

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract translation: 一种具有漏极区域（13,14）的横向DMOS晶体管，包括漏电极（D）与其接触的高浓度部分（14）和由沟道区域限定的低浓度部分（13） 。 除了传统的源极，漏极，主体和栅极之外，晶体管具有与漏极区域（13,14）的靠近沟道的低浓度部分的点接触的附加电极（25）。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。

公开(公告)号：EP2312329A1

公开(公告)日：2011-04-20

申请号：EP10187548.2

申请日：2010-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Selva, Carolina ,  Torelli, Cosimo

IPC: G01R31/3193 ,  G01R31/28

CPC classification number: G01R31/31935 ,  G01R31/2856

Abstract: A solution for executing a reliability test is proposed. A corresponding electronic device (100) includes functional means (110) for implementing a functionality of the electronic device, and testing means (115) for executing a test of the functional means including a plurality of test operations on the functional means; the testing means returns an indication of a result of each test operation. In the solution according to an embodiment of the invention, the electronic device further includes control means (125) for causing the testing means to reiterate the test, monitoring means (215) for monitoring the result of each test operation to detect a failure of the test operation, and storage means (130) for storing failure information indicative of temporal characteristics of each failure.

Abstract translation: 提出了一种用于执行可靠性测试的解决方案。 相应的电子设备（100）包括用于实现电子设备的功能的功能装置（110）和用于对功能装置执行多个测试操作的功能装置的测试的测试装置（115） 测试装置返回每个测试操作的结果的指示。 在根据本发明的实施例的解决方案中，电子设备还包括用于使测试装置重复测试的控制装置（125），用于监视每个测试操作的结果的监视装置（215）以检测 测试操作和用于存储指示每个故障的时间特征的故障信息的存储装置（130）。

公开(公告)号：EP0869506A1

公开(公告)日：1998-10-07

申请号：EP97830160.4

申请日：1997-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： Baroni, Andrea ,  Rimondi, Danilo ,  Taliercio, Michele ,  Torelli, Cosimo

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C7/14 ,  G11C11/419

Abstract: A memory device comprises an array (1) of memory cells (2,DMC0-DMCn) arranged in rows (R1-Rn) and columns (C1-Cm,DC), a plurality of gates (RD1-RDn) for transmitting respective selection outputs (RS1-RSn) of a row decoder (3) to respective rows (RS), a dummy column (DC) of dummy memory cells (DMC0-DMCn) substantially indentical to the memory cells, precharge means (P4,P5,P6,P7) for precharging the columns and the dummy column at a precharge potential (VDD) when no row is selected, and programming means (N7,N8,7) for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means (P3) for presetting the dummy memory cells in a first logic state when no row is selected; dummy column programming means (N9,N10) for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state; first detector means (DET1) for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of said gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from said first logic state to said second logic state.

Abstract translation: 存储器件包括排列成行（R1-Rn）和列（C1-Cm，DC）的存储器单元阵列（2，DMC-DMCn），用于传输各个选择的多个栅极（RD1-RDn） 行解码器（3）的输出（RS1-RSn）到各行（RS），与存储单元基本上不相邻的虚拟存储单元（DMC0-DMCn）的虚拟列（DC），预充电装置（P4，P5，P6 ，P7），用于在未选择行时将列和虚拟列预充电为预充电电位（VDD），以及用于在各个编程电位设置所选列的编程装置（N7，N8,7）。 该装置包括用于在没有行被选择时以第一逻辑状态预设虚拟存储器单元的伪存储单元预设装置（P3） 用于将虚拟列设置在与第一逻辑状态相反的第二逻辑状态对应的规定编程电位的虚拟列编程装置（N9，N10） 第一检测器装置（DET1），用于检测虚拟列已经从预充电电位放电到规定编程电位，并因此启用所述多个门。 每个所述门具有耦合到相应的虚拟存储器单元的输入，使得一旦所述虚拟存储器单元从所述第一逻辑状态切换到所述第二逻辑状态，所述门被禁用。

公开(公告)号：EP0865044A1

公开(公告)日：1998-09-16

申请号：EP97830107.5

申请日：1997-03-11

Applicant: STMicroelectronics S.r.l.

Inventor： Rimondi, Danilo ,  Torelli, Cosimo

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: A memory cell comprises a bistable element (I1,I2) with a first (A) and a second nodes (B) storing complementary data, first (N3) and second selection means (N4) for respectively coupling the first (A) and second nodes (B) to a first (0) and a second input/output nodes (0') of the memory cell (1). The first (N3) and second selection means (N4) are respectively controlled by independent first (WL r/w ) and second selection signals (WL w ).

Abstract translation: 存储单元包括具有第一（A）的双稳态元件（I1，I2）和存储互补数据的第二节点（B），第一（N3）和第二选择装置（N4）分别耦合第一（A）和第二 节点（B）到存储器单元（1）的第一（0）和第二输入/输出节点（0'）。 第一（N3）和第二选择装置（N4）分别由独立的第一（WLr / w）和第二选择信号（WLw）控制。

公开(公告)号：EP1936627A1

公开(公告)日：2008-06-25

申请号：EP07123373.8

申请日：2007-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Torelli, Cosimo ,  Rimondi, Danilo ,  Zappa, Rita

IPC: G11C5/14 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C5/14 ,  G11C11/417

Abstract: A monolithically integrated electronic system having a plurality of operating modes and comprising distinct random access static storage resources, acess to which is differently contemplated for different modes of operation, and means for interrupting power supply to distinct static storage resources that are not utilized in the currently selected operating mode, has two or more distinct static storage resources defined in distinct sectors of a single array of memory cells, each of which is separately powered through a dedicated supply line/source. All sectors share a single peripheral address and write/read circuitry that is also powered through a distinct supply line/source.
The on or off state of distinct sectors is determined via software and commanded by the running program of a certain application by the integrated electronic system.
A sector contemplated to remain always powered is composed by memory cells having a higher threshold of that of the memory cells of the other sectors of the array to be programmably switched off.

Abstract translation: 一种单片集成电子系统，其具有的操作模式的多元性和包含不同的随机接入的静态存储资源，接取所有被不同地预期用于不同的操作模式的装置，以及用于中断到确实未在当前使用的不同的静态存储资源电源 选择的操作模式，在存储器单元的单个阵列的不同扇区定义的两个或多个不同的静态存储资源，每一个的全部，其分别通过专用的供给线/电源供电。 所有扇区共享一个外设地址和读/写电路都IST通过不同的供应线/电源供电。 由集成电子系统通过软件的打开或关闭不同扇区的状态被确定的开采和由特定应用程序的运行的程序命令的。考虑到保持始终通电由具有做的存储器单元中的一个较高的阈值的存储单元构成的扇区 阵列的其他扇区被可编程地关闭。

公开(公告)号：EP1191601B1

公开(公告)日：2007-11-28

申请号：EP00830628.4

申请日：2000-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola ,  Atti, Massimo ,  Palumbo, Elisabetta ,  Torelli, Cosimo

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L29/7835

公开(公告)号：EP1624465A1

公开(公告)日：2006-02-08

申请号：EP04425617.0

申请日：2004-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Zappa, Rita ,  Selva, Carolina ,  Rimondi, Danilo ,  Torelli, Cosimo

IPC: G11C29/00

CPC classification number: G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device, including at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of predefined test algorithms, and a self-repair block that includes a column address generator processing the faulty addresses information for allocating redundant resources of the tested memory array, a redundancy register on which final redundancy information are loaded at each power-on of the device and a control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa, utilizes a single built-in self-test (BIST) structure serves any number of embedded memory arrays even of different type and size.
The built-in self-test and self-repair (BISR) structure further includes nonvolatile storage means containing information on addresses and data bus sizes of the device architecture, aspect ratio, capacity, multiplexing and scrambling parameters and relative test algorithm instructions for each of said embedded memory arrays and on which redundance column addresses are permanently stored and a multiple frequency clock generator for selecting the maximum operating clock frequency of the type of embedded memory array to be accessed.
Two distinct selectable test flows of an embedded random access memory array are selectable by programming. A first two-step test flow, each step of which includes the execution of a complete BIST check on the array, and a second three-step test flow, each step of which includes the execution of a complete BIST check on the array, the third BIST check revealing a possible failed programming of the redundance column addresses in said nonvolatile storage means.

Abstract translation: 甲内建自测试，并在集成设备中的嵌入式存储器阵列中的自修复结构（BISR），包括至少一个测试块（BIST）可编程的，以执行设备的任何特定数量的的respectivement存储器阵列 预定义的测试算法和一个自修复块做了包括上电设备的列地址发生器处理，以分配测试存储器阵列，其上最终冗余信息在每个加载的冗余寄存器的冗余资源的故障地址的信息和 用于管理从外部电路的数据传送到控制逻辑内置自测试和自修复结构（BISR），反之亦然，利用单个内建自测试（BIST）结构用于任何数目的嵌入式存储器阵列的 甚至不同的类型和大小。 该内建自测试和自修复（BISR）结构还包括非易失性存储装置，包含对每个的地址和设备架构的数据总线大小，长宽比，容量，复用和扰频参数和相对测试算法的指令信息 所述嵌入的存储器阵列和在其冗余列地址永久地存储和被访问，用于选择嵌入式存储器阵列的类型的最大工作时钟频率的倍数的频率的时钟发生器。 嵌入式随机存取存储器阵列的两个不同的可选择的测试流是由编程选择。 第一两步测试流，每个步骤都包括在阵列上的完整BIST检查的执行，和一个第二三步测试流，每个步骤都包括一个完整的BIST检查阵列上执行，所述 第三BIST检查揭示在所述非易失性存储装置中的冗余列地址的一个可能的编程失败。

公开(公告)号：EP1624464A1

公开(公告)日：2006-02-08

申请号：EP04425613.9

申请日：2004-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Selva, Carolina ,  Zappa, Rita ,  Rimondi, Danilo ,  Torelli, Cosimo ,  Mastrodomenico, Giovanni

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G11C29/16 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/3602

Abstract: A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them.
In practice, the BISD device diagnoses automatically memory arrays and allow to identify defects in the production process that affect a new technology during its learning phase, thus accelerating its "maturation".

Abstract translation: 用于随机存储器阵列的自诊断（BISD）装置优选地与随机存取存储器集成，执行一定数量的预定义的测试算法并识别故障位置的地址。 BISD设备识别感兴趣的某些故障模式并生成与它们相对应的位串。 在实践中，BISD设备自动诊断内存阵列，并允许在其学习阶段识别影响新技术的生产过程中的缺陷，从而加速其“成熟”。