公开(公告)号：EP1675181A1

公开(公告)日：2006-06-28

申请号：EP04425937.2

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Tessariol, Paolo ,  Bez, Roberto

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate (50), of STI isolation regions (shallow trench isolation) (57) filled by field oxide (65) and of memory cells (500) separated each other by said STI isolation regions (57). The memory cells (500) include a gate electrode (52) electrically isolated from said semiconductor material substrate (50) by a first dielectric layer (53), and the gate electrode includes a floating gate (54) self-aligned to the STI isolation regions (57). The method includes a formation phase of said floating gate (54) exhibiting a substantially saddle shape including a concavity; the formation phase of said floating gate (54) includes a deposition phase of a first conformal conductor material layer (54A).

Abstract translation: 一种制造非易失性MOS半导体存储器件的方法包括在半导体材料衬底（50）中由场氧化物（65）填充的STI隔离区域（浅沟槽隔离）（57））和存储器单元（ 500）通过所述STI隔离区域（57）彼此分离。 存储单元（500）包括通过第一介电层（53）与所述半导体材料基板（50）电隔离的栅电极（52），并且所述栅电极包括与所述STI隔离自对准的浮栅（54） 地区（57）。 该方法包括所述浮动栅极（54）的形成阶段，其显示包括凹部的基本鞍形; 所述浮置栅极（54）的形成阶段包括第一共形导体材料层（54A）的沉积阶段。