公开(公告)号：EP1786031A1

公开(公告)日：2007-05-16

申请号：EP05110577.3

申请日：2005-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Annese, Marco ,  Toia, Fabrizio Fausto ,  Montanini, Pietro

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28167 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/7834

Abstract: A vertical-gate MOS transistor ( 100 ) is proposed. The vertical-gate MOS transistor is integrated in a semiconductor chip ( 120 ) of a first conductivity type having a main surface, and includes an insulated trench gate ( 110 ) extending into the semiconductor chip from the main surface to a gate depth ( d1 ), said trench gate including a control gate ( G ) and an insulation layer ( 180 ) for insulating the control gate from the semiconductor chip, a source region and a drain region of a second conductivity type formed in the semiconductor chip, at least one of the source region and drain region being adjacent to the insulation layer and extending into the semiconductor chip from the main surface to a region depth ( d2 ) lower than the gate depth, wherein the insulation layer includes an external portion ( 180a ), extending into the semiconductor chip from the main surface to a protection depth ( d4 ) lower than the gate depth, and a remaining internal portion ( 180b ), the external portion having an external thickness ( d5 ) and the internal portion having an internal thickness ( d6 ) lower than the external thickness.

Abstract translation: 提出了垂直栅极MOS晶体管（100）。 垂直栅极MOS晶体管集成在具有主表面的第一导电类型的半导体芯片（120）中，并且包括从主表面延伸到栅极深度（d1）的半导体芯片中的绝缘沟槽栅极（110） 所述沟槽栅极包括控制栅极（G）和用于使控制栅极与半导体芯片绝缘的绝缘层（180），形成在半导体芯片中的第二导电类型的源极区域和漏极区域，至少一个 所述源极区域和漏极区域与所述绝缘层相邻并且从所述主表面延伸到所述半导体芯片中至低于所述栅极深度的区域深度（d2），其中所述绝缘层包括外部部分（180a），所述外部部分延伸到 半导体芯片从主表面到比栅极深度低的保护深度（d4），以及剩余内部部分（180b），外部部分具有外部厚度（d5）和i 内部部分具有比外部厚度低的内部厚度（d6）。