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    Integrated device with both SOI insulation and junction insulation and manufacturing method
    2.
    发明公开
    Integrated device with both SOI insulation and junction insulation and manufacturing method 审中-公开
    Integrierte Anordnung mit Isolation durch SOI und PN-Übergangund Herstellungsverfahren

    公开(公告)号：EP2264752A2

    公开(公告)日：2010-12-22

    申请号：EP10182985.1

    申请日：2006-06-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

    IPC: H01L21/74 ,  H01L21/84 ,  H01L29/06

    CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

    Abstract: A method is proposed for manufacturing an integrated electronic device (400) of the SOI type. The method includes the steps of providing an SOI substrate (105) including a semiconductor substrate (110), an insulating layer (115) on the semiconductor substrate, and a semiconductor starting layer (112) on the insulating layer, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (142) embedding the starting layer on the insulating layer, forming at least one insulating trench (405) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (415) and at least one further insulated region (425), and integrating components (420) of the device in the insulated regions; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (120) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, wherein each contact trench clears a corresponding portion (130b,130s) of the starting layer, of the insulating layer and of the substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material gettering impurities of the active layer, the gettered impurities in the at least one further insulated region being segregated from the insulated regions.

    Abstract translation: 提出了一种制造SOI型集成电子器件（400）的方法。 该方法包括以下步骤：提供包括半导体衬底（110），半导体衬底上的绝缘层（115）和绝缘层上的半导体起始层（112）的SOI衬底（105），执行外延生长工艺 ，外延生长工艺被施加到起始层，以获得将起始层嵌入绝缘层上的更厚的半导体有源层（142），形成从活性层的暴露表面延伸到至少一个绝缘沟槽（405） 绝缘层，所述至少一个绝缘沟槽将所述有源层分隔成绝缘区域（415）和至少一个另外的绝缘区域（425），以及将所述器件的部件（420）集成在所述绝缘区域中; 在根据本发明的实施例的解决方案中，该方法还包括在进行外延生长工艺的步骤之前，形成从起始层的暴露表面延伸到衬底的至少一个接触沟槽（120），对应于 每个另外的绝缘区域，其中每个接触沟槽清除起始层，绝缘层和衬底的对应部分（130b，130s），外延生长被进一步施加到清除部分，从而至少部分地填充每个接触沟槽 利用吸收有源层的杂质的半导体材料，至少一个另外的绝缘区域中的杂质杂质与绝缘区域分离。

    Process for the singulation of integrated devices in thin semiconductor chips
    3.
    发明公开
    Process for the singulation of integrated devices in thin semiconductor chips 审中-公开
    Prozess zur singulation integrierter Bauelemente indünnenHalbleiterchips

    公开(公告)号：EP2261969A1

    公开(公告)日：2010-12-15

    申请号：EP10185628.4

    申请日：2005-04-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ponza, Anna ,  Depetro, Riccardo ,  Montanini, Pietro

    IPC: H01L21/78

    CPC classification number: H01L21/78

    Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer (5') partially suspended above a semiconductor substrate (2) and constrained to the substrate (2) by temporary anchorages (10, 15'); dividing the layer (5') into a plurality of portions (13) laterally separated from one another; and removing the temporary anchorages (10, 15'; 38), in order to free the portions (13).

    Abstract translation: 用于制造半导体芯片中的集成器件的工艺设想：形成半导体衬底（2）部分悬置并通过临时锚固（10,15'）约束到衬底（2）的半导体层（5'）; 将层（5'）分成彼此横向分离的多个部分（13）; 以及移除所述临时锚固件（10,15'; 38），以便释放所述部分（13）。

    Method for manufacturing integrated structures including removing a sacrificial region
    4.
    发明公开
    Method for manufacturing integrated structures including removing a sacrificial region 失效
    用于制造包括去除牺牲区域的集成结构的方法

    公开(公告)号：EP0922944A2

    公开(公告)日：1999-06-16

    申请号：EP98830266.7

    申请日：1998-04-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

    IPC: G01L9/00

    CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

    Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region (6) of silicon oxide on a substrate (1) of semiconductor material; growing a pseudo-epitaxial layer (8); forming an electronic circuit (10-13, 18); depositing a silicon carbide layer (21); defining photolithographycally the silicon carbon layer so as to form an etching mask (23) containing the topography of a microstructure (27) to be formed; with the etching mask (23), forming trenches (25) in the pseudo-epitaxial layer (8) as far as the sacrificial region (6) so as to laterally define the microstructure; and removing the sacrificial region (6) through the trenches (25).

    Abstract translation: 该方法基于使用碳化硅掩模去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底（1）上形成氧化硅的牺牲区域（6） 生长伪外延层（8）; 形成电子电路（10-13,18）; 沉积碳化硅层（21）; 定义光刻硅碳层以形成包含待形成的微结构（27）的形貌的蚀刻掩模（23） 利用蚀刻掩模（23），在伪外延层（8）中形成直至牺牲区域（6）的沟槽（25）以横向地限定微结构; 并通过沟槽（25）去除牺牲区域（6）。

    Integrated angular speed sensor device and production method thereof
    5.
    发明公开
    Integrated angular speed sensor device and production method thereof 失效
    Integrierter Winkelgeschwindigkeitssensor und Verfahren zu seiner Herstellung

    公开(公告)号：EP0911606A1

    公开(公告)日：1999-04-28

    申请号：EP97830537.3

    申请日：1997-10-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Foroni, Mario ,  Ferrera, Marco ,  Montanini, Pietro

    IPC: G01C19/56

    CPC classification number: G01C19/574 ,  G01C19/5769 ,  G01P15/0802 ,  H01L21/76202 ,  H01L21/764

    Abstract: The angular speed sensor comprises a pair of mobile masses (2a, 2b) which are formed in the epitaxial layer (37) and are anchored to one another and to the remainder of the device by anchorage elements; the mobile masses are symmetrical with one another, and have mobile excitation electrodes (6a) which are intercalated with respective fixed excitation electrodes (7a 1 , 7a 2 ) and mobile detection electrodes (6b) which are intercalated with fixed detection electrodes (7b 1 , 7b 2 ). The mobile and fixed excitation electrodes extend in a first direction and the mobile and fixed detection electrodes extend in a second direction which is perpendicular to the first direction and is disposed on a single plane parallel to the surface of the device.

    Abstract translation: 角速度传感器包括一对移动质量块（2a，2b），它们形成在外延层（37）中，并通过锚定元件相互锚定并固定到装置的其余部分; 移动质量彼此对称，并且具有插入有固定的检测电极（7b1,7b2）的固定激励电极（7a1,7a2）和移动检测电极（6b）的移动激励电极（6a）。 移动和固定激励电极沿第一方向延伸，并且移动和固定检测电极在垂直于第一方向的第二方向上延伸并且设置在平行于装置表面的单个平面上。

    Integrated device with both SOI insulation and junction insulation and manufacturing method
    6.
    发明公开
    Integrated device with both SOI insulation and junction insulation and manufacturing method 审中-公开
    具有SOI绝缘和接合绝缘的集成器件和制造方法

    公开(公告)号：EP2264753A2

    公开(公告)日：2010-12-22

    申请号：EP10183038.8

    申请日：2006-06-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

    IPC: H01L21/74 ,  H01L21/84 ,  H01L29/06

    CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

    Abstract: A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

    Abstract translation: 提出了一种用于制造集成电子设备（500）的方法。 该方法包括以下步骤：提供包括半导体衬底（510），在半导体衬底上的绝缘层（515）以及在绝缘层上的半导体起始层（512）的SOI衬底（505），衬底和起始 所述外延生长工艺被施加到所述起始层以获得在所述绝缘层上嵌入所述起始层的第一类型的导电性的更厚的半导体活性层（542） 形成从有源层的暴露表面延伸到绝缘层的至少一个绝缘沟槽（558），所述至少一个绝缘沟槽将有源层分隔成绝缘区域（560）和至少一个另外的绝缘区域（561）， 以及将所述器件的部件（580）集成在所述绝缘区域中，所述部件通过所述绝缘层与所述衬底绝缘; 在根据本发明实施例的解决方案中，所述方法还包括：在执行外延生长工艺的步骤之前，形成至少一个接触沟槽（520），所述接触沟槽从起始层的暴露表面延伸到衬底， 每个另外的绝缘区域，每个接触沟槽清除起始层，绝缘层和衬底的对应部分（530b，530s）;将不同于第一类型的第二类型导电性的掺杂物注入至少部分 其中外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充每个接触沟槽，掺杂剂在外延生长期间扩散以形成第二类型导电性的绝缘区域（545） 每个另外的绝缘区域的至少一个接触沟槽，并且还将每个进一步的器件的组件（580）集成在一起 所述另外的部件在反向偏置时通过由所述对应的绝缘区域与所述有源层和/或所述衬底形成的结与所述衬底绝缘。

    Waveguide manufacturing method and waveguide
    8.
    发明公开
    Waveguide manufacturing method and waveguide 审中-公开
    Wellenleiter和Verfahren zur Herstellung eines Wellenleiters

    公开(公告)号：EP1435533A1

    公开(公告)日：2004-07-07

    申请号：EP02425811.3

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Di Turi, Luigi ,  Favretto, Ivana ,  Mottura, Marta

    IPC: G02B6/12

    CPC classification number: G02B6/136 ,  G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B2006/12173

    Abstract: A method of producing a waveguide (20) with a rounded core integrated in a substrate (1), including phases of:

    forming a lower cladding (3) of the guide supported by the substrate;
    etching said lower cladding to define a concave region delimited by a curved surface (11) and extending along the axis of propagation;
    providing on a free surface (12) of said lower cladding a layer (13) of doped material filling the concave region (4) to form a first portion (17) of the core in contact with the curved surface;
    etching the layer of doped material so that only sufficient volume of doped material for the waveguide core remains;
    heating the doped material so that it forms a rounded core due to surface tension and the concave region of the cladding.

    Abstract translation: 一种制造具有集成在衬底（1）中的圆形芯的波导（20）的方法，包括：形成由衬底支撑的引导件的下包层（3）; 蚀刻所述下部包层以限定由弯曲表面（11）限定并沿着传播轴线延伸的凹形区域; 在所述下包层的自由表面（12）上提供填充所述凹区（4）的掺杂材料层（13），以形成与所述弯曲表面接触的所述芯的第一部分（17）; 蚀刻掺杂材料层，使得仅剩余足够体积的用于波导芯的掺杂材料; 加热掺杂的材料，使得它由于表面张力和包层的凹形区域而形成圆形芯。

    Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced
    10.
    发明公开
    Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced 失效
    一种用于制造其以这样的方式制造高灵敏度的积分的加速度计和陀螺仪传感器和传感器的方法

    公开(公告)号：EP0895090A1

    公开(公告)日：1999-02-03

    申请号：EP97830407.9

    申请日：1997-07-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Montanini, Pietro ,  Ferrera, Marco

    IPC: G01P15/08 ,  G01P15/125

    CPC classification number: H01L21/764 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00246 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0735 ,  B81C2203/0778 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/76202

    Abstract: To increase the sensitivity of the sensor, the movable mass (40) forming the seismic mass is formed starting from the epitaxial layer (13) and is covered by a weighting region of tungsten (26c) which has high density. To manufacture it, buried conductive regions (2) are formed in the substrate (1); then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions (9a-9d) are formed on the buried conductive regions (2) so as to cover them partially; the epitaxial layer (13) is then grown, using a nucleus region; a tungsten layer (26) is deposited and defined and, using a silicon carbide layer (31) as mask, the suspended structure (40) is defined; finally the sacrificial region is removed, forming an air gap (38).

    Abstract translation: 为了提高传感器的灵敏度，在形成振动质量运动质量块（40）形成由具有高密度的外延层（13）和由钨（26C）的加权区域覆盖开始。 为了制造它，掩埋的导电区域（2）在基片（1）形成; 然后，在在Sametime，牺牲区域在可动质量将要形成与氧化物绝缘区域（图9A-9D）是在掩埋的导电区域形成的区域（2）形成，以覆盖它们的部分; 然后在外延层（13）上生长，使用核区; 钨层（26）沉积和定义，并使用碳化硅层（31）作为掩模，对悬挂结构（40）所定义; 最后牺牲区域被移除，在空气间隙（38）形成。

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