公开(公告)号：EP1881505A1

公开(公告)日：2008-01-23

申请号：EP06425503.7

申请日：2006-07-20

Applicant: STMicroelectronics S.r.l.

Inventor： Mondello, Antonino ,  Tumminia, Alessandro ,  Buono, Luigi

IPC: G11C29/16 ,  G11C29/00

CPC classification number: G11C29/48 ,  G11C16/04 ,  G11C29/16 ,  G11C29/4401 ,  G11C29/82

Abstract: An automatic redundancy system exploits and existent microprocessor management system on chip for carrying out autonomously, without communicating with the external test machine, the operations of writing data in the memory array according to one or more pre-established test patterns, of verifying data successively read from the memory array, eventually of substituting failed elements of the array with equivalent redundancy structures. A logic structure detects and stores eventual array fails upstream of the output data path, thus speeding up data collection relating to eventual fails without any interaction with the EWS test machine apart from communicating the end of the execution of the redundancy process.

Abstract translation: 一种自动冗余系统攻击和在芯片上用于自主执行现有微处理器管理系统，不与外部测试机，写入数据的操作的存储器阵列中的雅丁连通到一个或多个预先确定的测试图案，核实数据的顺序读出 从存储器阵列，最终与代等效冗余结构阵列的不合格元件。 逻辑结构检测并存储最终的阵列的输出数据路径的上游发生故障，从而加快数据采集与最终失败，而不与EWS测试机除了通信的冗余处理的执行结束的任何相互作用。