公开(公告)号：EP3623341A1

公开(公告)日：2020-03-18

申请号：EP19196770.2

申请日：2019-09-11

Applicant: STMicroelectronics S.r.l.

Inventor： COSTANTINI, Sonia ,  ASSANELLI, Davide ,  BORTOLOTTI, Aldo Luigi ,  VIMERCATI, Michele ,  VARISCO, Igor

IPC: B81C1/00

Abstract: A manufacturing process comprising the steps of: forming a bottom semiconductor region (130) including a main sub-region (131), which extends through a bottom dielectric region (112_bot, 114_bot) that coats a semiconductor wafer (100), and a secondary sub-region (134), which coats the bottom dielectric region and surrounds the main sub-region; forming a first top cavity (140) and a second top cavity (142) through the wafer, delimiting a fixed body (145, 146, 148, 154, 155) and a patterned structure (151, 152, 153) that includes a central portion (151), which contacts the main sub-region, and deformable portions (152, 153), in contact with the bottom dielectric region; forming a bottom cavity (180) through the bottom semiconductor region, as far as the bottom dielectric region, the bottom cavity laterally delimiting a stiffening region (191) that includes the main sub-region and leaving exposed parts of the bottom dielectric region that contact the deformable portions and parts of the bottom dielectric region that delimit the first and second top cavities; and selectively removing the parts left exposed by the bottom cavity.