公开(公告)号：EP3208940A1

公开(公告)日：2017-08-23

申请号：EP16191058.3

申请日：2016-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： ZELLA, Daniele ,  POLETTO, Vanni ,  FOPPIANI, Mauro

IPC: H03K17/687

CPC classification number: H03K17/6872 ,  G05F3/26 ,  H03K17/60 ,  H03K17/687

Abstract: In one embodiment, a (pre)driver circuit (10) includes first (10a) and a second (10b) output terminal for driving electronic switches, such as e.g. MOSFETs (S) including a control terminal (GN, GP) and a e.g. source-drain current path through the switch (SN, SP), the arrangement admitting:
- one or more first driving configurations (e.g. for PMOS), with the first (10a) and second (10b) output terminals are coupled to the current path (SP) and the control electrode (GP) of the electronic switch (S), respectively, and
- one or more second driving configurations (e.g. for NMOS, both HS and LS), wherein the first (10a) and second (10b) output terminals of the driver circuit (10) are coupled to the control electrode (GN) and the current path (SN) of the electronic switch, respectively.

Abstract translation: 在一个实施例中，（预）驱动器电路（10）包括用于驱动电子开关的第一（10a）和第二（10b）输出端子，例如， 包括控制端子（GN，GP）的MOSFET（S） 通过开关（SN，SP）的源极 - 漏极电流路径，该布置允许： - 一个或多个第一驱动配置（例如用于PMOS），第一（10a）和第二（10b）输出端子耦合到电流路径 （S）的控制电极（GP）和一个或多个第二驱动配置（例如用于NMOS，HS和LS两者），其中第一（10a）和第二（10b） 驱动器电路（10）的输出端子分别耦合到电子开关的控制电极（GN）和电流路径（SN）。

公开(公告)号：EP3208940B1

公开(公告)日：2018-12-05

申请号：EP16191058.3

申请日：2016-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： ZELLA, Daniele ,  POLETTO, Vanni ,  FOPPIANI, Mauro

IPC: G05F3/26 ,  H03K17/60 ,  H03K17/687

CPC classification number: H03K17/6872 ,  G05F3/26 ,  H03K17/60 ,  H03K17/687

Abstract: In one embodiment, a (pre)driver circuit (10) includes first (10a) and a second (10b) output terminal for driving electronic switches, such as e.g. MOSFETs (S) including a control terminal (GN, GP) and a e.g. source-drain current path through the switch (SN, SP), the arrangement admitting: - one or more first driving configurations (e.g. for PMOS), with the first (10a) and second (10b) output terminals are coupled to the current path (SP) and the control electrode (GP) of the electronic switch (S), respectively, and - one or more second driving configurations (e.g. for NMOS, both HS and LS), wherein the first (10a) and second (10b) output terminals of the driver circuit (10) are coupled to the control electrode (GN) and the current path (SN) of the electronic switch, respectively.