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公开(公告)号：EP4137366A2
公开(公告)日：2023-02-22
申请号：EP22190946.8
申请日：2022-08-18
Applicant: STMicroelectronics S.r.l.
Inventor： ARGENTO, Davide , PENNISI, Orazio , CASTORINA, Stefano , POLETTO, Vanni , LANDINI, Matteo , MAINO, Andrea
IPC: B60R21/017 , G01R27/26 , G01R31/00 , G01R31/64 , B60R21/01
Abstract: A system and method for measuring a capacitance value of a capacitor (102) are provided. In embodiments, a resistor (112) is coupled to a terminal of the capacitor (102). A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor (102) is measured. The discharge routine includes sinking a current through a discharge circuit (108, 110) coupled to the resistor (112) from first to second. Integration of a difference in voltage at terminals of the resistor (112) during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor (112). The health of the capacitor (102) is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：EP3208940A1
公开(公告)日：2017-08-23
申请号：EP16191058.3
申请日：2016-09-28
Applicant: STMicroelectronics S.r.l.
Inventor： ZELLA, Daniele , POLETTO, Vanni , FOPPIANI, Mauro
IPC: H03K17/687
CPC classification number: H03K17/6872 , G05F3/26 , H03K17/60 , H03K17/687
Abstract: In one embodiment, a (pre)driver circuit (10) includes first (10a) and a second (10b) output terminal for driving electronic switches, such as e.g. MOSFETs (S) including a control terminal (GN, GP) and a e.g. source-drain current path through the switch (SN, SP), the arrangement admitting:
- one or more first driving configurations (e.g. for PMOS), with the first (10a) and second (10b) output terminals are coupled to the current path (SP) and the control electrode (GP) of the electronic switch (S), respectively, and
- one or more second driving configurations (e.g. for NMOS, both HS and LS), wherein the first (10a) and second (10b) output terminals of the driver circuit (10) are coupled to the control electrode (GN) and the current path (SN) of the electronic switch, respectively.Abstract translation: 在一个实施例中，（预）驱动器电路（10）包括用于驱动电子开关的第一（10a）和第二（10b）输出端子，例如， 包括控制端子（GN，GP）的MOSFET（S） 通过开关（SN，SP）的源极 - 漏极电流路径，该布置允许： - 一个或多个第一驱动配置（例如用于PMOS），第一（10a）和第二（10b）输出端子耦合到电流路径 （S）的控制电极（GP）和一个或多个第二驱动配置（例如用于NMOS，HS和LS两者），其中第一（10a）和第二（10b） 驱动器电路（10）的输出端子分别耦合到电子开关的控制电极（GN）和电流路径（SN）。
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3.发明公开
公开(公告)号：EP4386437A1
公开(公告)日：2024-06-19
申请号：EP23307132.3
申请日：2023-12-05
Inventor： LETOR, Romeo , RUSSO, Alfio , LECCI, Nadia , PIZZARDI, Antonio Filippo Massimo , PAVLIN, Antoine , POLETTO, Vanni , BRERA, Marco , BIANCHI, Simone
CPC classification number: G01S7/4815 , G01S7/484 , G01S17/10 , H01S5/0428 , G01S7/4817 , H01S5/4031
Abstract: In a driver circuit (100) couplable to laser diodes (LD_j), a semiconductor body (504) has a first surface (504a). A first control switch (S1) has a drain (DS1) coupled to a drain metallization (530) and a source (SS1) coupled to a first source metallization (532). The drain metallization is couplable to a power supply line (12). A second control switch (S1_0) has a drain (DS1_0) coupled to the drain metallization and a source (SS1_0) coupled to a second source metallization (533) . The first and second source metallizations are couplable to cathode terminals of the laser diodes (LD_j) and to a reference node (GND). A plurality of high-side switches (S2_j) have respective drains (DS2_j) coupled to the drain metallization (530) and respective sources (SS2_j) coupled to respective third source metallizations (534_j). Each third source metallization (534_j) is coupled to a respective drive output node (13_j) for driving an anode terminal (LDa_j) of a respective laser diode (LD_j). The drain metallization as well as the first, second and third source metallizations face the first surface (504a) of the semiconductor body (504), which is also configured to face the laser diodes (LD_j). The second source metallization (533) and the third source metallizations (534_j) are aligned with one another in a direction of alignment (540) and are superimposed, orthogonally to the direction of alignment (540), to the respective source terminals of the second control switch (S1_0) and of the high-side switches (S2_j).
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公开(公告)号：EP4300766A1
公开(公告)日：2024-01-03
申请号：EP23305969.0
申请日：2023-06-19
Inventor： POLETTO, Vanni , PAVLIN, Antoine
Abstract: In an embodiment, a phase circuit (300) includes: a bidirectional output stage (321) configured to be coupled between a first battery (104) and a second battery (106); a memory (310) configured to store a number of active phases, and an identifier; and a synchronization circuit (306) configured to receive a first clock signal (S PWM_CLK ) and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal (S PWM_CLK ), where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.
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5.发明公开
公开(公告)号：EP4250561A1
公开(公告)日：2023-09-27
申请号：EP23159134.8
申请日：2023-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： ROGLEDI, Nicola , POLETTO, Vanni , LEONE, Antonio Davide
Abstract: A circuit arrangement of an amplifier with currentcontrolled gain, said circuit arrangement (30; 40; 50) having a symmetrical differential structure, comprising a differential input stage (21), which includes, on each differential branch, an input transistor, in particular a MOSFET (M1, M2), coupled, in particular through an input resistance ( R I ), to an input node (NI), there being set between said input node (N1) and ground (GND) a current generator (22) for biasing the input stage (21) that supplies, said input stage (21) being configured for operating with a constant input biasing, an input voltage (Vin) being applied between the inputs of the input transistors (M1, M2), a drain electrode of the input transistor (M1) being coupled to the supply voltage (Vss) through a respective diode (D1, D2), as well as to a differential output amplification stage (23) having bipolar transistors (T1, T2) with coupled emitters, there being coupled to said emitters a current generator (24) for biasing the output stage (23, 33) which generates an output current ( I bOUT ) and comprises, on each differential branch, a bipolar transistor (T1, T2; B2) biased in the active region, the base electrode of which is coupled to the drain electrode of the input transistor (M1, M2) and the collector electrode of which is coupled to the supply voltage (Vss), while coupled to its emitter electrode is a current generator (24) for biasing the output stage (23, 33) which generates an output current ( I bOUT ) , an output voltage (Vout) being drawn from between the collectors of the bipolar transistors (T1, T2), said output stage (23, 33) being configured with constant output biasing,
said circuit arrangement being configured for controlling a gain between the input and the output by controlling the values of input and output biasing current;
said circuit arrangement (30) being configured for supplying a first reference current ( I d ) and a second reference current ( I n ) having complementary values such that their sum is constant, the value of said input biasing current ( I bIN ) corresponding to the first reference current ( I d ), and the output biasing current ( I bOUT ) corresponding to the sum ( I d + I n ) of said first reference current ( I d ) and said second reference current ( I n ).-
Patent Agency Ranking6.发明公开
公开(公告)号：EP4207604A1
公开(公告)日：2023-07-05
申请号：EP22211363.1
申请日：2022-12-05
Applicant: STMicroelectronics S.r.l.
Inventor： POLETTO, Vanni , ROGLEDI, Nicola , LEONE, Antonio Davide
Abstract: An analog to digital converter apparatus, adapt to receive a continuous input signal (Vdiff; Vi+,V-,i+,i-),
comprising an integrating block (11; 11, 12), comprising at least an integrating stage, which output is coupled to a flash analog to digital converter (13; 33),
said analog to digital converter apparatus comprising a feedback path (15; 151, 152; 35; 351, 352) coupled to the output (DO) of said flash analog to digital converter (13; 33), said feedback path comprising at least a digital to analog conversion block (15; 151, 152; 35; 351, 352) which output (Vfeed; II, 12) is compared (21; 21, 22) at least to the input signal (Vdiff; Vi+,V-,i+,i-) to obtain an error signal (Ev; Ev; Ev2) which is brought as input to said integrating block (11; 11, 12),
wherein a control block (34) configured to perform a control comprising at least a digital integration (343), is coupled between the output of said flash analog to digital converter (33) and said feedback path (35; 351, 352).-
公开(公告)号：EP3937318A1
公开(公告)日：2022-01-12
申请号：EP21305838.1
申请日：2021-06-18
Inventor： LETOR, Romeo , POLETTO, Vanni , PAVLIN, Antoine , LECCI, Nadia , RUSSO, Alfio
Abstract: A pulse generator circuit, for driving a laser diode (LD) in a LIDAR system, for instance, comprises a first node (10) and a second node (12) to apply a pulse signal to an electrical load (LD) as well as a first electronic switch (HSD) coupled between the first node (10) and the second node (12) and a second electronic switch (LSD) coupled between the second node (12) and a reference node (GND). An LC resonant circuit (Lr, Cr) comprising an inductance (Lr) and a capacitance (Cr) is coupled between the first node (10) and the reference node (GND) along with charge circuitry (100) coupled between a supply node (VCC) and an intermediate node (16) in the LC resonant circuit (Lr, Cr).
Drive circuitry (14, 141, 142) of the electronic switches (HSD, LSD) repeats during a sequence of switching cycles charge time intervals, wherein the capacitance (Cr) in the LC resonant circuit (Lr, Cr) is charged via the charge circuit (100), and pulse generation time intervals, wherein a pulsed current is provided to the load (LD) via the first node (10) and the second node (12). The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit (Lr, Cr) oscillates at a resonance frequency.
The charge circuitry comprises a further inductance (L Charge) in a current flow line between the supply node (VCC) and the intermediate node (16) in the LC resonant circuit (Lr, Cr).-
公开(公告)号：EP3926348A1
公开(公告)日：2021-12-22
申请号：EP21178626.4
申请日：2021-06-09
Applicant: STMicroelectronics S.r.l.
Inventor： POLETTO, Vanni , ERRICO, Nicola , VILMERCATI, Paolo , CIGNOLI, Marco , GENNA, Vincenzo Salvatore , ALAGNA, Diego
IPC: G01R19/00 , G01R19/165 , H02M1/00
Abstract: A circuit (100') comprises a high-side switch (HS) and a low-side switch (LS) arranged between a supply node (D) and a reference node (G), the high-side and low-side switches having an intermediate node (Q). A switching control signal ( com ) is applied with opposite polarities to the high-side and low-side switches. An inductive load (L) is coupled between the intermediate node (Q) and one of said supply node (D) and said reference node (G).
The circuit (100') further comprises current sensing circuitry (CS') configured to:
sample (12a, 14a) a first value ( I a ) of the load current flowing in one of the high-side and low-side switches at a first sampling instant ( t 1 ) before a commutation ( t s ) of the switching control signal ( com ),
sample (12b, 14b) a second value ( I b ) of the load current flowing in the other of the high-side and low-side switches at a second sampling instant ( t 2 ) after said commutation ( t s ) of said switching control signal ( com ),
sample (12b, 14c) a third value ( I c ) of the load current flowing in the other of the high-side and low-side switches at a third sampling instant ( t 3 ) after said second sampling instant ( t 2 ), and
generate (18) a failure signal ( fail ) as a function of said first ( I a ), second ( I b ) and third ( I c ) sampled values of the load current.-
公开(公告)号：EP3203247A1
公开(公告)日：2017-08-09
申请号：EP16191022.9
申请日：2016-09-28
Applicant: STMicroelectronics S.r.l.
Inventor： POLETTO, Vanni , ROGLEDI, Nicola
IPC: G01R27/14
CPC classification number: G01R27/14
Abstract: A device for measuring an unknown resistance (R X ), comprising a reference resistance (R REF ) in series with the unknown resistance (R X ). The device is prearranged for measuring a first voltage (V1) and a second voltage (V2), across the reference resistance (R REF ) and of the unknown resistance (R X ), respectively.
The device comprises changeover-switch modules (muxA, muxB), which receive at input the first voltage (V1) and the second voltage (V2) and supply values (D1, D2) representing the first voltage (V1) and the second voltage (V2), and a single analog-to-digital converter (ADC), which supplies at output the digital representation (D X ) of the value of the unknown resistance (R X ) as ratio between the values (D1, D2) at input to the converter (ADC). The analog-to-digital converter (ADC) contains two negative feedback loops (D2, D1), which function in an alternative way according to the outputs of the changeover-switch modules (muxA, muxB). The negative feedback loops (D2, D1) are first-order continuous-time sigma-delta converters. In particular, one of the two sigma-delta converters has a constant digital output at the level "1".Abstract translation: 一种测量未知电阻（RX）的装置，包括与未知电阻（RX）串联的参考电阻（RREF）。 该装置被预先设定用于分别跨参考电阻（RREF）和未知电阻（RX）测量第一电压（V1）和第二电压（V2）。 该装置包括在输入端接收第一电压（V1）和第二电压（V2）以及表示第一电压（V1）和第二电压（V1）的电源值（D1，D2）的切换开关模块（muxA，muxB） V2）和单个模数转换器（ADC），其在输出端提供未知电阻值（RX）的数字表示（DX），作为输入端处的值（D1，D2）与 转换器（ADC）。 模数转换器（ADC）包含两个负反馈环路（D2，D1），根据转换开关模块（muxA，muxB）的输出以另一种方式工作。 负反馈回路（D2，D1）是一阶连续时间Σ-Δ转换器。 特别是，两个西格玛 - 德尔塔转换器中的一个在水平“1”处具有恒定的数字输出。
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公开(公告)号：EP4170906A1
公开(公告)日：2023-04-26
申请号：EP22199382.7
申请日：2022-10-03
Applicant: STMicroelectronics S.r.l.
Inventor： CIGNOLI, Marco , POLETTO, Vanni
Abstract: A circuit, comprising at least one switching transistor (Q LS , Q HS ) having a control terminal configured to receive a control signal (X) as well as a current flow path therethrough, the at least one switching transistor (Q LS , Q HS ) configured to be switched towards a conductive, resp. non-conductive, state in response to the control signal (X) having a first, resp. second, value wherein the current flow path through the at least one switching transistor (Q LS , Q HS ) provides a current flow line (I QLS , I QHS ) between a switching circuit node (VO) and a reference node (VI, PGND), wherein, in the non-conductive state, a voltage drop stress is applied across the at least one switching transistor (Q LS , Q HS ).
The circuit comprises a sense transistor (M LS ) coupled to the least one switching transistor (Q LS , Q HS ) and being a scaled replica thereof, the sense transistor (M LS ) having a current sense flow path therethrough wherein the intensity of the current (I MS ) flowing therein is indicative of the intensity of the current (I QLS , I QHS ) flowing in the current flow path through the at least one switching transistor (Q LS , Q HS ), and coupling circuitry (13, SB, S 1 , S 2 , S 3 , S 4 ) configured to apply the voltage drop stress across the sense transistor (M LS ) in response to the at least one switching transistor (Q LS , Q HS ) being switched towards the non-conductive state, wherein, in response to the at least one switching transistor (Q LS , Q HS ) being switched towards the non-conductive state, the voltage drop stress is replicated across both the at least one switching transistor (Q LS , Q HS ) and across the sense transistor (M LS , M SH ).
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