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    Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages
    1.
    发明授权
    Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages 失效
    在同一半导体芯片上集成具有不同阈值电压的MOS技术的装置的方法

    公开(公告)号：EP0915509B1

    公开(公告)日：2005-12-28

    申请号：EP97830543.1

    申请日：1997-10-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Bolognesi, Davide ,  Magri', Angelo

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10

    CPC classification number: H01L29/7802 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238

    Abstract: Process for integrating in a same MOS technology devices with different threshold voltages, characterized by comprising the steps of: simultaneously forming on a semiconductor material layer (2,2') of at least two gate electrodes (5,5';10,10') for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area; selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions (7;7') for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density for unit area and on the aperture angles of the corner of the respective gate electrodes.

    Asymmetric MOS technology power device
    2.
    发明授权
    Asymmetric MOS technology power device 失效
    非对称MOS技术功率器件

    公开(公告)号：EP0817274B1

    公开(公告)日：2004-02-11

    申请号：EP96830384.2

    申请日：1996-07-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magri', Angelo ,  Zambrano, Raffaele ,  Frisina, Ferruccio

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

    Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

    Power MOS device and corresponding manufacturing method
    3.
    发明公开
    Power MOS device and corresponding manufacturing method 有权
    MOS-Leistungsanordnung und entsprechendes Herstellungsverfahren

    公开(公告)号：EP1659638A1

    公开(公告)日：2006-05-24

    申请号：EP05025288.1

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magri', Angelo ,  Frisina, Ferruccio ,  Ferla, Giuseppe

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712

    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors (2) having respective gate structures (12) and comprising a gate oxide (7) with double thickness having a thick central part (8) and lateral portions (9) of reduced thickness. Such device exhibiting gate structures (12) comprising first gate conductive portions (13) overlapped onto said lateral portions (9) of reduced thickness to define, for the elementary Mos transistors (2), the gate electrodes, as well as a conductive structure or mesh (14). Such conductive structure (14) comprising a plurality of second conductive portions (15) overlapped onto the thick central part (8) of gate oxide (7) and interconnected to each other and to the first gate conductive portions (13) by means of a plurality of conducive bridges (16). The present invention further relates to a method for realising the power MOS device.

    Abstract translation: 该功率MOS器件包括具有各自的栅极结构（12）的多个基本功率MOS晶体管（2），并且包括具有厚度为中心部分（8）的厚度的双层厚度的栅极氧化物（7）和侧壁部分 减小厚度。 这种具有栅极结构（12）的器件包括第一栅极导电部分（13），该第一栅极导电部分重叠在所述侧面部分（9）上以减小厚度，以限定基本的MOS晶体管（2），栅极电极以及导电结构 网格（14）。 这种导电结构（14）包括多个第二导电部分（15），其重叠在栅极氧化物（7）的厚的中心部分（8）上并且通过一个第二栅极导电部分（13）彼此互连并连接到第一栅极导电部分 多个有利桥梁（16）。 本发明还涉及实现功率MOS器件的方法。

    Vertical power semiconductor device and method of making the same
    4.
    发明公开
    Vertical power semiconductor device and method of making the same 有权
    Vertikale Leistungshalbleiteranordnung und Verfahren zu deren Herstellung

    公开(公告)号：EP1643558A1

    公开(公告)日：2006-04-05

    申请号：EP04425733.5

    申请日：2004-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferrucio ,  Ferla, Giuseppe ,  Magri', Angelo

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08

    CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

    Abstract: A vertical conduction electronic power device and corresponding realisation method, the device being integrated on a semiconductor substrate (10) and comprising respective gate (20), source (25) and drain (30) areas, realised in an epitaxial layer (40) arranged on said semiconductor substrate (10) and comprising respective gate (21), source (26) and drain (31) metallisations realised by means of a first metallisation level as well as gate (60), source and drain (70) terminals or pads realised by means of a second metallisation level. The device is configured as a set of modular areas (100) extending parallel to each other, each having a rectangular elongate source area (25) perimetrically surrounded by a narrow gate area (20), and separated from each other by regions (30a) with drain area (30) extending parallel and connected at the opposite ends thereof to a second closed region (30b) with drain area (30) forming a device outer peripheral edge; as well as a sinker structure (45) extending perpendicularly to the substrate and formed by a grid of sinker (S) located below both the first parallel regions (30a) and the second closed region (30b) with drain area (30) in order to favour a conductive channel for a current coming from the source area (25) and directed towards the drain area (30) across the substrate (10).

    Abstract translation: 一种垂直传导电子功率器件及相应的实现方法，该器件集成在半导体衬底（10）上并且包括在外延层（40）中实现的相应的栅极（20），源极（25）和漏极（30） 在所述半导体衬底（10）上并且包括相应的栅极（21），借助于第一金属化级别实现的源极（26）和漏极（31），以及栅极（60），源极和漏极（70）端子或焊盘 通过第二金属化水平实现。 该装置被配置为一组彼此平行延伸的模块化区域（100），每组具有由狭窄的栅极区域（20）围绕周边的矩形细长的源区域（25），并且由区域（30a）彼此分离， 其中漏区30在其相对端平行延伸并连接到具有形成器件外周边缘的漏区（30）的第二闭合区（30b）; 以及垂直于衬底延伸并由位于两个第一平行区域（30a）和第二闭合区域（30b）下方的沉降片（S）的栅格形成的沉降片结构（45），排列区域（30）依次排列有排水区域 有利于来自源极区域（25）的电流的导电通道，并且穿过衬底（10）引导到漏极区域（30）。

    Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages
    5.
    发明公开
    Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages 失效
    在同一半导体芯片上集成具有不同阈值电压的MOS技术的装置的方法

    公开(公告)号：EP0915509A1

    公开(公告)日：1999-05-12

    申请号：EP97830543.1

    申请日：1997-10-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Bolognesi, Davide ,  Magri', Angelo

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10

    CPC classification number: H01L29/7802 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238

    Abstract: Process for integrating in a same MOS technology devices with different threshold voltages, characterized by comprising the steps of: simultaneously forming on a semiconductor material layer (2,2') of at least two gate electrodes (5,5';10,10') for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area; selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions (7;7') for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density for unit area and on the aperture angles of the corner of the respective gate electrodes.

    Abstract translation: 在具有不同阈值电压，通过包括以下步骤为特征的一个相同的MOS技术的设备工艺处理INTEGRA婷：“至少两个栅电极（5,5的半导体材料层（2,2）”上同时形成; 10,10' ），用于至少两个MOS器件，所述栅极电极包含基本上为直线的部分和角落，具有用于单位面积的respectivement角密度每个栅电极; 在该半导体材料层有选择地将掺杂剂为respectivement沟道区的同时形成（7; 7“），用于所述至少两个MOS器件中，respectivement栅电极之下延伸到所述沟道区域，所述选择性地引入使用作为掩模respectivement 栅电极，从而所述信道区具有，在respectivement栅电极的角部中，掺杂剂浓度比在基本为直线的部分低的，并且所述两个MOS器件因此具有respectivement的阈值电压也依赖于角密度为单位面积和 在栅电极respectivement的角部的孔径角。

    Vertical MOS device and method of making the same
    7.
    发明公开
    Vertical MOS device and method of making the same 审中-公开
    垂直MOS器件和它们的制备方法

    公开(公告)号：EP1455397A3

    公开(公告)日：2005-08-17

    申请号：EP03029916.8

    申请日：2003-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

    Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).
    The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps: realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and realising an enrichment region (9) in the JFET area below the thicker layer.

    MOS technology power device
    9.
    发明公开
    MOS technology power device 审中-公开
    MOS-TECHNOLOGIE-Leistungsanordnung

    公开(公告)号：EP1160873A1

    公开(公告)日：2001-12-05

    申请号：EP00830360.4

    申请日：2000-05-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Saggio, Mario ,  Frisina, Ferruccio ,  Magri', Angelo

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36

    CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634

    Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and apart (1) of said power device which is placed between zones where the elementary active units are formed. The part (1) of the power device comprises at least two heavily doped body regions (4) of a first conductivity type which are formed in a semiconductor layer (3) of a second conductivity type, a first lightly doped semiconductor region (5) of the first conductivity type which is placed laterally between the two body regions (4). The first semiconductor region (5) is placed under a succession of a thick silicon oxide layer (9), a polysilicon layer (10) and a metal layer (13). A plurality of second lightly doped semiconductor regions (6) of the first conductivity type are placed under said at least two heavily doped body regions (4) and under said first lightly doped semiconductor region (5) of the first conductivity type, each region (6) of said plurality of second lightly doped semiconductor regions (6) of the first conductivity type being separated from the other by portions of said semiconductor layer (3) of the second conductivity type.

    Abstract translation: 描述了一种MOS技术功率器件，其包括多个基本有源单元，并且分离（1）所述功率器件，放置在形成基本有源单元的区域之间。 功率器件的部分（1）包括形成在第二导电类型的半导体层（3）中的至少两个第一导电类型的重掺杂体区域（4），第一轻掺杂半导体区域（5） 的横向放置在两个主体区域（4）之间的第一导电类型。 第一半导体区域（5）被放置在厚氧化硅层（9），多晶硅层（10）和金属层（13）的一连串之下。 第一导电类型的多个第二轻掺杂半导体区域（6）放置在所述至少两个重掺杂体区域（4）的下方，并且位于第一导电类型的所述第一轻掺杂半导体区域（5）的下方，每个区域 所述第一导电类型的所述多个第二轻掺杂半导体区域（6）的所述第二导电类型的所述半导体层（3）的一部分与所述第二导电类型的所述多个第二轻掺杂半导体区域（6）分离。

    Power MOS semiconductor device
    10.
    发明授权
    Power MOS semiconductor device 有权
    MOS功率半导体器件

    公开(公告)号：EP1659636B1

    公开(公告)日：2009-11-04

    申请号：EP05025285.7

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferruccio, Frisina ,  Ferla, Giuseppe ,  Magri', Angelo ,  Grimaldi, Antonio Giuseppe ,  Bazzano, Gaetano

    IPC: H01L29/78 ,  H01L29/49

    CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983

    Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors (2) and a gate structure (12) comprising a plurality of conductive strips (8) realised with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks (11) connected to a gate pad (30) and at least a connection layer (20) arranged in series to at least one of said conductive strip (8). Such gate structure (12) comprising at least a plurality of independent islands (10) formed on the upper surface (9) of the conductive strips (8) and suitably formed on the connection layers (20). Said islands (10) being realised with at least one second conductive material such as silicide.

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