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    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    1.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件的方法，特别是相变存储器，所述方法包括硅化

    公开(公告)号：EP1439579A9

    公开(公告)日：2005-02-09

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Phase change memory cell and manufacturing method thereof using minitrenches
    2.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    Phasenwechsel-Speicherzelle sowie deren Herstellungsverfahren手套Minigräben

    公开(公告)号：EP1339110A1

    公开(公告)日：2003-08-27

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一尺寸的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一薄部分（22）和第二薄部分（38a）直接电接触并限定亚光刻延伸部分的接触区域（58）。 第二薄部分（38a）由限定光刻开口（51）的模制层（49）围绕的氧化物间隔部分（55a）横向限定。 间隔物部分（55a）通过间隔物形成技术在形成光刻开口之后形成。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    4.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件，特别是相变存储器，具有硅化方法

    公开(公告)号：EP1439579A1

    公开(公告)日：2004-07-21

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Abstract translation: 的方法worin到绝缘区域（13）在一个主体中形成至少围绕到一半导体主体的阵列部分（51）（10）; 半导体材料的栅极区（16）形成在所述半导体主体的一个电路部分（51）的顶部（10）; 的第一硅化物保护掩模（52）是形成在阵列部分的顶部上; 栅极区（16）和所述电路部（51）的有源区（43）被硅化并且所述第一硅化物保护掩模（52）被去除。 第一硅化物保护掩模（52）是多晶硅，并且与所述栅极区域（16）同时形成。 覆盖所述第一硅化物保护掩模（52）的介电材料的第二硅化物保护掩模（53）的栅极区（16）的硅化之前形成。 第二硅化物保护掩模（53）与形成尾盘反弹到栅极区域（16）间隔件（41）同时形成。

    Phase change memory cell and manufacturing method thereof using minitrenches
    5.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元，并且借助于minitrenches及其制造方法

    公开(公告)号：EP1339110A9

    公开(公告)日：2004-01-28

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

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