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    Phase change memory cell and manufacturing method thereof using minitrenches
    1.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    Phasenwechsel-Speicherzelle sowie deren Herstellungsverfahren手套Minigräben

    公开(公告)号：EP1339110A1

    公开(公告)日：2003-08-27

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一尺寸的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一薄部分（22）和第二薄部分（38a）直接电接触并限定亚光刻延伸部分的接触区域（58）。 第二薄部分（38a）由限定光刻开口（51）的模制层（49）围绕的氧化物间隔部分（55a）横向限定。 间隔物部分（55a）通过间隔物形成技术在形成光刻开口之后形成。

    Small area contact region, high efficiency phase change memory cell and fabrication method thereof
    3.
    发明公开
    Small area contact region, high efficiency phase change memory cell and fabrication method thereof 审中-公开
    小面积接触区域，高效率相变存储器元件及其制造方法

    公开(公告)号：EP1318552A1

    公开(公告)日：2003-06-11

    申请号：EP01128461.9

    申请日：2001-12-05

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Riva, Caterina ,  Zonca, Romina

    IPC: H01L45/00 ,  G11C11/34 ,  H01L27/24

    CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

    Abstract: A contact structure (30) in an electronic semiconductor device, including a first conducting region (31) having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region (32) having a second thin portion (32a) with a second sublithographic dimension in a second direction transverse to said first direction; the first and second conducting regions being in direct electrical contact at the first and second thin portions and defining a contact area (33) having a sublithografic extension, lower than 100 nm, preferably about 20 nm. The thin sublithographic portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer (34); the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic hard mask opening that is used to etch a mold opening (40) in a mold layer (38) and filling the mold opening.

    Abstract translation: 在半导体电子器件，其包括具有在第一方向上的第一亚光刻尺寸的第一薄壁部的第一导电区域（31）的接触结构（30）; 具有在第二方向上横向于所述第一方向的第二亚光刻尺寸的第二薄壁部（32A）的第二导电区（32）; 第一和第二导电区域在所述第一和第二薄膜部分直接电接触和限定具有sublithografic延伸的接触区域（33），低于100nm，优选约20nm。薄亚光刻的部分获得使用沉积代替 光刻的：所述第一薄壁部的设置于在第一电介质层（34）中的开口的壁; 所述第二薄壁部是通过在第一划界层的垂直壁罢免牺牲区域，在所述牺牲区域的自由侧罢免第二划界层，去除牺牲区域以形成亚光刻硬掩模开口获得并用于蚀刻 在模制层（38）和填充所述模具开口的模具开口（40）。

    Process for forming a thin film of TiSiN, in particular for phase change memory devices
    7.
    发明公开
    Process for forming a thin film of TiSiN, in particular for phase change memory devices 有权
    HerstellungdünnerSchichten aus TiSiN，besondersfürPhasenwechselspeicher

    公开(公告)号：EP1482551A1

    公开(公告)日：2004-12-01

    申请号：EP03425337.7

    申请日：2003-05-26

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Zonca, Romina

    IPC: H01L21/768

    CPC classification number: H01L45/06 ,  H01L21/76841 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

    Abstract: The process for forming a film of TiSiN includes the following sequence of steps: deposition of a TiN film at medium temperature, for example, 300-450°C, by thermal decomposition of a metallorganic precursor, for example TDMAT (Tetrakis Dimethylamino Titanium); exposition to a silicon releasing gas, such as silane (SiH 4 ) and dichlorine-silane (SiH 2 Cl 2 ) at 10-90 sccm -standard cube centimeters per minute- for a quite long time, for example, longer than 10 s but less than 90 s, preferably about 40 s; exposition to a H 2 /N 2 plasma at 200-800 sccm, for 10-90 s, preferably about 40 s.

    Abstract translation: 制备钛，硅和氮（TiSiN）络合物的膜包括：（a）沉积TiN（钛氮）膜; 和（b）将钛和氮复合物（TiN）的膜暴露于硅释放气体，而不预先将膜暴露于碳还原处理。

    Phase change memory cell and manufacturing method thereof using minitrenches
    8.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元，并且借助于minitrenches及其制造方法

    公开(公告)号：EP1339110A9

    公开(公告)日：2004-01-28

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof
    9.
    发明公开
    Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof 有权
    集成电阻元件，其具有用于其制备这样的电阻元件和过程的相变存储器元件

    公开(公告)号：EP1331675A1

    公开(公告)日：2003-07-30

    申请号：EP02425013.6

    申请日：2002-01-17

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Zonca, Romina ,  Marangon, Maria Santina ,  De Santi, Giorgio

    IPC: H01L45/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: A vertical-current-flow resistive element (12) comprising a monolithic region (12) having a first portion (12a) and a second portion (12b) arranged on top of one another and formed by a single material. The first portion has a first resistivity, and the second portion (12b) has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion (12a) is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion (12a) than in the second portion (12b). Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi 2 , Ta, WSi, and the increase in resistivity is obtained by nitridation.

    Abstract translation: 的垂直电流流电阻元件（12）包括具有第一部分（12a）和（12b）的布置在彼此的顶部上，并通过一个单一的材料形成的第二部分的单片区域（12）。 所述第一部分具有第一电阻率，并且所述第二部分（12b）具有第二电阻率，比所述第一电阻率。 为了这个目的，具有均匀的电阻率和高度比其他尺寸首先形成的至少一个大的整体区域; 然后所述第一部分（12a）的电阻率是通过引入，从顶部增加，物种确实形成具有单片区域的导电材料的普遍地共价键，所以没有所述物质的浓度变得在第一部分更高（12A ）比（在第二部分12b）。 优选地，导电材料是二元或三元合金，从TiAl金属，的TiSi2，钽，的WSi选自，和电阻率的增加是由氮化获得。

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