公开(公告)号：EP1865655A8

公开(公告)日：2008-04-16

申请号：EP07104629.6

申请日：2007-03-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Bertoni, Guido ,  Owen, Jefferson E.

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0631 ,  H04L9/0637 ,  H04L9/3242 ,  H04L2209/125 ,  H04L2209/24 ,  H04L2209/38 ,  H04L2209/80

Abstract: The invention concerns Circuitry for encrypting at least a part of an input data (Bi) flow and generating a tag based on said input data flow with a same ciphering algorithm and a same key (K), said algorithm comprising iterative computations by at least two operation units, said circuitry comprising a pipeline comprising: an input selection unit (612) arranged to receive first data values to generate encryption sequences with said ciphering algorithm, second data values to generate temporary tags with said ciphering algorithm and an output of the pipeline; a first stage (627) arranged to receive an output of said input selection unit and comprising at least a first operation unit (632); and a second stage (635) arranged to receive an output of the first stage, comprising at least a second operation unit (648) and providing said output of the pipeline.

公开(公告)号：EP1865654A8

公开(公告)日：2008-04-16

申请号：EP07104627.0

申请日：2007-03-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Bertoni, Guido ,  Owen, Jefferson E.

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0631 ,  H04L9/0637 ,  H04L9/3242 ,  H04L2209/125 ,  H04L2209/24 ,  H04L2209/38 ,  H04L2209/80

Abstract: The invention concerns circuitry for encrypting at least a part of an input data (Bi) flow and generating a tag based on said input data flow with a same ciphering algorithm and a same key comprising: a first ciphering branch arranged to encrypt said at least part of said input data; a second ciphering branch arranged to generate said tag; and a single key schedule unit arranged to receive said key, to generate at least one sub-key based on said key and to provide said at least one sub-key to said first and second ciphering branches.

公开(公告)号：EP1865654A1

公开(公告)日：2007-12-12

申请号：EP07104627.0

申请日：2007-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bertoni, Guido ,  Owen, Jefferson E.

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0631 ,  H04L9/0637 ,  H04L9/3242 ,  H04L2209/125 ,  H04L2209/24 ,  H04L2209/38 ,  H04L2209/80

Abstract: The invention concerns circuitry for encrypting at least a part of an input data (Bi) flow and generating a tag based on said input data flow with a same ciphering algorithm and a same key comprising: a first ciphering branch arranged to encrypt said at least part of said input data; a second ciphering branch arranged to generate said tag; and a single key schedule unit arranged to receive said key, to generate at least one sub-key based on said key and to provide said at least one sub-key to said first and second ciphering branches.

Abstract translation: 本发明涉及用于加密输入数据（Bi）流的至少一部分并基于所述输入数据流以相同的加密算法和相同的密钥生成标签的电路，包括：第一加密分支，被布置为加密所述至少部分 的所述输入数据; 布置成生成所述标签的第二加密分支; 以及单个密钥调度单元，被配置为接收所述密钥，以基于所述密钥生成至少一个子密钥，并向所述第一和第二加密分支提供所述至少一个子密钥。

公开(公告)号：EP2416523A1

公开(公告)日：2012-02-08

申请号：EP11173633.6

申请日：2011-07-12

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Bertoni, Guido ,  Sozzani, Fabio

IPC: H04L9/22

CPC classification number: H04L9/0662 ,  H04L2209/125

Abstract: L'invention concerne un procédé de chiffrement ou de déchiffrement d'un flux de données binaires, comprenant des étapes de génération d'un flux binaire de chiffrement (BS) et de combinaison par une opération logique réversible de chaque bit du flux de données binaires à un bit du flux binaire de chiffrement, la génération du flux binaire de chiffrement comprend des étapes consistant à : générer un bloc d'entrée (CB1, CB2, CB3) en appliquant une fonction cryptographique (ENC1, ENC2, ENC3) utilisant une clé secrète (SK) à un bloc (RN, CB1, CB2), et générer le flux binaire de chiffrement à partir du bloc d'entrée en combinant entre eux les bits du bloc d'entrée par des opérations logiques, de manière à éviter que le bloc d'entrée puisse être déterminé à partir du flux binaire de chiffrement uniquement.

Abstract translation: 该方法涉及生成加密二进制流（BS1-BSn），并且通过可逆逻辑运算将二进制数据流的每一位与加密二进制流的位组合。 通过使用秘密密钥（SK）将加密函数应用于数据块（RN）并通过组合每个输入块的比特来生成来自输入块的加密二进制流来生成输入块（CB1-CB3）来生成加密二进制流 通过逻辑操作输入块，以避免仅从加密二进制流确定输入块。 还包括用于包括加密二进制流生成电路的流加密装置的独立权利要求。

公开(公告)号：EP1865655A1

公开(公告)日：2007-12-12

申请号：EP07104629.6

申请日：2007-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bertoni, Guido ,  Owen, Jefferson E.

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0631 ,  H04L9/0637 ,  H04L9/3242 ,  H04L2209/125 ,  H04L2209/24 ,  H04L2209/38 ,  H04L2209/80

Abstract: The invention concerns Circuitry for encrypting at least a part of an input data (Bi) flow and generating a tag based on said input data flow with a same ciphering algorithm and a same key (K), said algorithm comprising iterative computations by at least two operation units, said circuitry comprising a pipeline comprising: an input selection unit (612) arranged to receive first data values to generate encryption sequences with said ciphering algorithm, second data values to generate temporary tags with said ciphering algorithm and an output of the pipeline; a first stage (627) arranged to receive an output of said input selection unit and comprising at least a first operation unit (632); and a second stage (635) arranged to receive an output of the first stage, comprising at least a second operation unit (648) and providing said output of the pipeline.

Abstract translation: 本发明涉及用于加密至少一部分输入数据（Bi）流并基于所述输入数据流以相同的加密算法和相同密钥（K）生成标签的电路，所述算法包括至少两次的迭代计算 所述电路包括：流水线，包括：输入选择单元，被配置为接收第一数据值以产生具有所述加密算法的加密序列;第二数据值，用于利用所述加密算法生成临时标签和输出管道; 布置成接收所述输入选择单元的输出并且至少包括第一操作单元（632）的第一级（627）; 以及布置成接收第一级的输出的第二级（635），包括至少第二操作单元（648）并提供管道的所述输出。